摘要:
A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches.
摘要:
A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.
摘要:
A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.
摘要:
One exemplary method of assigning addresses in two or more address spaces with address fields of different lengths comprises defining address types, assigning a value to first bits at the high ends of the address fields to identify a first said address type, assigning second bits at the low ends of the address fields to identify addresses of the first said address type, and inserting different numbers of additional bits between the first bits and the second bits in the two or more address spaces.
摘要:
A SCI controller manages responses and requests between SCI interconnection rings and memory access controllers. The SCI controller includes a request activation queue that stores information about the requests until the SCI rings have the resources to handle the requests. The controller also has a response activation queue that stores information about the responses until the memory access controller is accessible. The queues do not store the request and response packets, but rather store information that is used to construct the request and response packets. The SCI controller also has a contents addressable memory or CAM that checks for an address match between the current requests and responses and previous requests and responses. A table stores more specific information about the previous requests.
摘要:
A method of providing hardware description language-embedded regular expression support for module iteration and interconnection. Regular expressions such as those used in the Perl programming language are used in a preprocessing process to generate instances and interconnections in a hardware description to automate the generation of repetitive code for a Hardware Description Language (HDL). This is accomplished by generating HDL code with embedded regular expressions, analyzing the code to identify the regular expressions and checking to see that the code complies with the HDL grammar rules. A data structure is generated for each module or submodule and these data structures are then elaborated to expand them into the instances and interconnections. A text generator traverses the elaborated data structures and generates HDL compliant text.
摘要:
A system for building checksums efficiently builds a checksum of various data values that are stored in different memory units of a computer system. During the checksum build process, data stores to the memory locations storing the various data values are enabled, thereby enabling the checksum to be built without significantly impacting the performance of the computer system.
摘要:
In general, a system and method is provided for dynamically reallocating computer memory. A mapper receives requests to access data. The requests include bus addresses, and the mapper maps the bus addresses to memory unit addresses based on a plurality of mappings maintained by the mapper. The memory unit addresses identify a plurality of memory locations including a destination memory location and a source memory location. Data requested by the requests received by the mapper is accessed based on the memory unit addresses mapped from the bus addresses included in the requests. When desired, a data value from the source memory location is dynamically moved to the destination memory location, and the mappings are updated such that a bus address mapped to a memory unit address identifying the source memory location is instead mapped to a memory unit address identifying the destination memory location.
摘要:
A system for storing and retrieving data utilizes a plurality of memory units having memory locations for storing data values. A checksum of a plurality of the data values in a particular checksum set is maintained in one of the memory locations. One of the plurality of data values can be recovered by combining each of the remaining plurality of data values with the checksum. After retrieving one of the plurality of data values during the data recovery process, steps are taken to ensure that any further attempts to access the location of the retrieved data value do not cause an update to the checksum. Therefore, the locations storing the data values of the checksum set may be accessed (e.g., read from or written to) during the data recovery process without causing errors to the data recovery process.
摘要:
The system and method for performing an update operation on the sharing list in a multi-node SCI-based system involves issuing an update command from a first node in the list to the remaining nodes in the sharing list, however the first node maintains its position at a head position in the sharing list. The first node issues an increment command to each successive node in the list until the end of the list is reached. Each node receives the increment command and updates its cache and then sends a reply back to the first node, listing the state of the node and a pointer to the next node. The method and system also prevents a node from rolling out of the sharing list before that node receives the update command. Each node has a phase value that is toggled as the node is incremented. Thus, a rollout request will be nullified unless the phase value of the rollout request matches the phase value of the node. The system and method also interlocks the rollout requests to inhibit a node that is being rolled out from being incremented.