公开(公告)号：US20190296150A1

公开(公告)日：2019-09-26

申请号：US16436939

申请日：2019-06-11

Applicant: DELTA ELECTRONICS, INC.

Inventor： Chao-Feng CAI ,  Jian-Hong ZENG ,  Zeng LI ,  Xiao-Ni XIN

IPC: H01L29/78 ,  H01L23/50 ,  H01L23/00

Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

公开(公告)号：US20160181788A1

公开(公告)日：2016-06-23

申请号：US14813140

申请日：2015-07-30

Applicant: DELTA ELECTRONICS, INC.

Inventor： Zeng LI ,  Chao-Feng CAI

IPC: H02H3/28 ,  H03K17/687

CPC classification number: H03K17/0828 ,  H03K17/567 ,  H03K17/6871 ,  H03K2017/6875

Abstract: A cascode switch device includes a cascode circuit, which includes a first switch and a second switch, and a protection circuit. The protection circuit is coupled between the first switch and the second switch. A first leakage current passing through the protection circuit is greater than or equal to a difference between a second leakage current and a third leakage current, and is smaller than an upper limit value of a leakage current of the cascode circuit. An upper limit value of a withstanding voltage is present between the first terminal and the control terminal of the first switch. When the first switch operates at the upper limit value of the withstanding voltage, the second leakage current is an upper limit value of a leakage current passing through the first switch, and the third leakage current is a lower limit value of a leakage current passing through the second switch.

Abstract translation: 共射共同开关装置包括共源共栅电路，其包括第一开关和第二开关以及保护电路。 保护电路耦合在第一开关和第二开关之间。 通过保护电路的第一漏电流大于或等于第二泄漏电流和第三漏电流之间的差，并且小于共源共栅电路的漏电流的上限值。 在第一开关的第一端子和控制端子之间存在耐受电压的上限值。 当第一开关工作在耐受电压的上限值时，第二漏电流是通过第一开关的漏电流的上限值，第三漏电流是通过的漏电流的下限值 第二个开关。

公开(公告)号：US20160293755A1

公开(公告)日：2016-10-06

申请号：US15077927

申请日：2016-03-23

Applicant: DELTA ELECTRONICS, INC.

Inventor： Chao-Feng CAI ,  Jian-Hong ZENG ,  Zeng LI

IPC: H01L29/78 ,  H01L23/48 ,  H01L23/538 ,  H01L23/50

CPC classification number: H01L29/7826 ,  H01L23/50 ,  H01L24/20 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2924/19104

Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

Abstract translation: 半导体封装结构包括芯片，第一引脚，第二引脚和第三引脚。 芯片包括第一表面，第二表面，第一电源开关和第二开关，并且第一电源开关和第二开关都包括第一端子和第二端子。 芯片的第二表面与芯片的第一表面相对。 第一个引脚不与第二个引脚接触。 芯片的第一电源开关的第一端子耦合到第一引脚，芯片的第一电源开关的第二端子耦合到第三引脚。 芯片的第二电源开关的第一端子耦合到第三引脚，芯片的第二电源开关的第二端子耦合到第二引脚。

公开(公告)号：US20170309746A1

公开(公告)日：2017-10-26

申请号：US15647278

申请日：2017-07-12

Applicant: DELTA ELECTRONICS, INC.

Inventor： Chao-Feng CAI ,  Jian-Hong ZENG ,  Zeng LI

IPC: H01L29/78 ,  H01L23/50

CPC classification number: H01L29/7826 ,  H01L23/50 ,  H01L24/20 ,  H01L24/24 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/7816 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2924/19104

Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.