SIGNAL OUTPUT CIRCUIT
    2.
    发明申请

    公开(公告)号:US20210111682A1

    公开(公告)日:2021-04-15

    申请号:US17130011

    申请日:2020-12-22

    Inventor: Takahisa Koyasu

    Abstract: A signal output circuit includes an inverting amplifier circuit, a feedback capacitor and a low pass filter. The inverting amplifier circuit includes an input terminal and an output terminal. The inverting amplifier circuit executes an inverting amplification based on an input signal to output a signal to the output terminal at a pull-up state. An output stage of the inverting amplifier circuit is an open collector or an open drain. The feedback capacitor is connected between the input terminal and the output terminal of the inverting amplifier circuit. The low pass filter has an input and an output. The input of the low pass filter is connected to the output terminal of the inverting amplifier. The output of the low pass filter is connected to the feedback capacitor.

    Communication circuit apparatus and transceiver having the same
    3.
    发明授权
    Communication circuit apparatus and transceiver having the same 有权
    通信电路设备和收发器具有相同的功能

    公开(公告)号:US09106459B2

    公开(公告)日:2015-08-11

    申请号:US14322108

    申请日:2014-07-02

    Inventor: Takahisa Koyasu

    Abstract: A communication circuit apparatus includes: multiple level shift circuits, each of which receives an input signal corresponding to a respective communication bus; an activation comparator for generating an activation signal when the input signal is input into one of the level shift circuits, and a level of the input signal exceeds a predetermined threshold; multiple input current voltage conversion circuits, each of which is arranged together with a respective level shift circuit, converts the input signal to a voltage signal, and outputs the voltage signal as an identification signal; and an identification circuit for identifying one of the communication busses based on the identification signal, which is output from one of the input current voltage conversion circuits. The one of the communication busses corresponds to the one of the level shift circuits, in which the input signal is input.

    Abstract translation: 通信电路装置包括:多个电平移位电路,每个电平移位电路接收对应于各个通信总线的输入信号; 激活比较器,用于当所述输入信号被输入到所述电平移位电路之一时产生激活信号,并且所述输入信号的电平超过预定阈值; 多个输入电流电压转换电路,各自与各个电平移位电路一起布置,将输入信号转换为电压信号,并输出电压信号作为识别信号; 以及识别电路,用于基于从一个输入电流电压转换电路输出的识别信号来识别通信总线中的一个。 通信总线中的一个对应于输入信号被输入的电平移位电路之一。

    Signal output circuit
    4.
    发明授权

    公开(公告)号:US11451202B2

    公开(公告)日:2022-09-20

    申请号:US17130011

    申请日:2020-12-22

    Inventor: Takahisa Koyasu

    Abstract: A signal output circuit includes an inverting amplifier circuit, a feedback capacitor and a low pass filter. The inverting amplifier circuit includes an input terminal and an output terminal. The inverting amplifier circuit executes an inverting amplification based on an input signal to output a signal to the output terminal at a pull-up state. An output stage of the inverting amplifier circuit is an open collector or an open drain. The feedback capacitor is connected between the input terminal and the output terminal of the inverting amplifier circuit. The low pass filter has an input and an output. The input of the low pass filter is connected to the output terminal of the inverting amplifier. The output of the low pass filter is connected to the feedback capacitor.

    Drive control device
    5.
    发明授权

    公开(公告)号:US09948285B2

    公开(公告)日:2018-04-17

    申请号:US15045763

    申请日:2016-02-17

    Abstract: A drive control device includes: an input unit of a command; and a control unit setting a period for rising a current in an inductive load to first and third periods in first and second commands, and setting a period for falling the current to second and fourth periods in the first and second commands, respectively. When the first command is changed to the second command, and at least one middle PMW pulse is disposed between a forward PWM pulse corresponding to the first command and an after PWM pulse corresponding to the second command, the control unit sets fifth and sixth periods in the middle PWM pulse corresponding to the first and second periods of the forward PWM pulse to a length between the first and second periods in the forward PWM pulse and the third and fourth periods in the after PWM pulse, respectively.

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