公开(公告)号：US20060228842A1

公开(公告)日：2006-10-12

申请号：US11101354

申请日：2005-04-07

申请人： Da Zhang ,  Jing Liu ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

发明人： Da Zhang ,  Jing Liu ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/338 ,  H01L21/20

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

摘要翻译： 半导体制造工艺包括形成覆盖在半导体衬底（102）上的栅电介质（110）上的栅电极（120）。 第一间隔物（124）形成在栅电极（120）的侧壁上。 使用栅电极（120）和第一间隔物（124）作为掩模，在基板（102）中形成第一s / d沟槽（130）。 第一s / d沟槽（130）填充有第一s / d结构（132）。 第二间隔物（140）形成在邻近第一间隔物（124）的栅电极（120）侧壁上。 使用栅电极（120）和第二间隔物（140）作为掩模，在衬底（102）中形成第二s / d沟槽（150）。 第二s / d沟槽（150）填充有第二s / d结构（152）。 填充第一和第二s / d沟槽（130,150）优选地包括使用外延工艺来生长s / d结构。 s / d结构（132,152）可以是应力诱导结构，例如用于PMOS晶体管的硅锗和用于NMOS晶体管的硅碳。

公开(公告)号：US20060068553A1

公开(公告)日：2006-03-30

申请号：US10954121

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam Sadaka ,  Ted White ,  Alexander Barr ,  Venkat Kolagunta ,  Bich-Yen Nguyen ,  Victor Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam Sadaka ,  Ted White ,  Alexander Barr ,  Venkat Kolagunta ,  Bich-Yen Nguyen ,  Victor Vartanian ,  Da Zhang

IPC分类号： H01L21/336

CPC分类号： H01L21/2254 ,  H01L29/665 ,  H01L29/66787 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78648

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

摘要翻译： 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

公开(公告)号：US20060030093A1

公开(公告)日：2006-02-09

申请号：US10913099

申请日：2004-08-06

申请人： Da Zhang ,  Brian Goolsby ,  Eric Luckowski ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

发明人： Da Zhang ,  Brian Goolsby ,  Eric Luckowski ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/8234

CPC分类号： H01L29/7842 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/78687

摘要： A method for forming at least a portion of a semiconductor device includes providing a substrate and epitaxially forming an etch stop layer over the substrate. A first layer is provided over the etch stop layer, wherein the first layer is selectively etchable with regard to the etch stop layer. A structure is provided over a region of the first layer, wherein the region is not all of the first layer. In addition, the method includes etching at least a portion of the first layer that is outside of the region, wherein the etch stop layer is used an as etch stop. A strained layer is epitaxially grown in the etch-recessed region.

摘要翻译： 用于形成半导体器件的至少一部分的方法包括提供衬底并在衬底上外延地形成蚀刻停止层。 第一层设置在蚀刻停止层上方，其中第一层相对于蚀刻停止层可选择性地蚀刻。 在第一层的区域上提供结构，其中该区域不是全部第一层。 此外，该方法包括蚀刻位于该区域之外的第一层的至少一部分，其中蚀刻停止层用作蚀刻停止。 在蚀刻凹陷区域中外延生长应变层。

公开(公告)号：US20060065927A1

公开(公告)日：2006-03-30

申请号：US10952676

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam Sadaka ,  Ted White ,  Alexander Barr ,  Venkat Kolagunta ,  Bich-Yen Nguyen ,  Victor Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam Sadaka ,  Ted White ,  Alexander Barr ,  Venkat Kolagunta ,  Bich-Yen Nguyen ,  Victor Vartanian ,  Da Zhang

IPC分类号： H01L29/06

CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78687

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

摘要翻译： 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

公开(公告)号：US07226820B2

公开(公告)日：2007-06-05

申请号：US11101354

申请日：2005-04-07

申请人： Da Zhang ,  Jing Liu ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted R. White

发明人： Da Zhang ,  Jing Liu ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted R. White

IPC分类号： H01L21/00

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

摘要翻译： 半导体制造工艺包括形成覆盖在半导体衬底（102）上的栅电介质（110）上的栅电极（120）。 第一间隔物（124）形成在栅电极（120）的侧壁上。 使用栅电极（120）和第一间隔物（124）作为掩模，在基板（102）中形成第一s / d沟槽（130）。 第一s / d沟槽（130）填充有第一s / d结构（132）。 第二间隔物（140）形成在邻近第一间隔物（124）的栅电极（120）侧壁上。 使用栅电极（120）和第二间隔物（140）作为掩模，在衬底（102）中形成第二s / d沟槽（150）。 第二s / d沟槽（150）填充有第二s / d结构（152）。 填充第一和第二s / d沟槽（130,150）优选地包括使用外延工艺来生长s / d结构。 s / d结构（132,152）可以是应力诱导结构，例如用于PMOS晶体管的硅锗和用于NMOS晶体管的硅碳。

公开(公告)号：US20070235807A1

公开(公告)日：2007-10-11

申请号：US11742955

申请日：2007-05-01

申请人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

发明人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66772

摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

摘要翻译： 在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。 衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。 底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。 然后在氧掺杂半导体层上外延生长半导体层。 在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。 然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。 不同类型的晶体管形成在不同的结晶取向上。

公开(公告)号：US20070190745A1

公开(公告)日：2007-08-16

申请号：US11351518

申请日：2006-02-10

申请人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

发明人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/823807 ,  H01L21/76264 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  Y10S438/973

摘要： A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.

公开(公告)号：US20060228851A1

公开(公告)日：2006-10-12

申请号：US11093801

申请日：2005-03-30

申请人： Mariam Sadaka ,  Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Shawn Thomas ,  Ted White

发明人： Mariam Sadaka ,  Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Shawn Thomas ,  Ted White

IPC分类号： H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

摘要翻译： 根据本公开的实施例，制造双应变通道半导体器件的过程包括将应变Si和压缩SiGe与沟槽隔离相集成，以实现同时的NMOS和PMOS性能增强。 如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

公开(公告)号：US20050181549A1

公开(公告)日：2005-08-18

申请号：US10780143

申请日：2004-02-17

申请人： Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

发明人： Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04

CPC分类号： H01L27/1203 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84

摘要： A first semiconductor structure has a silicon substrate, a first silicon germanium layer grown on the silicon, a second silicon germanium layer on the first silicon germanium layer, and a strained silicon layer on the second silicon germanium layer. A second semiconductor structure has a silicon substrate and an insulating top layer. The silicon layer of the first semiconductor structure is bonded to the insulator layer to form a third semiconductor structure. The second silicon germanium layer is cut to separate most of the first semiconductor structure from the third semiconductor structure. The silicon germanium layer is removed to expose the strained silicon layer where transistors are subsequently formed, which is then the only layer remaining from the first semiconductor structure. The transistors are oriented along the direction and at a 45 degree angle to the direction of the base silicon layer of the second silicon.

摘要翻译： 第一半导体结构具有硅衬底，在硅上生长的第一硅锗层，第一硅锗层上的第二硅锗层和第二硅锗层上的应变硅层。 第二半导体结构具有硅衬底和绝缘顶层。 第一半导体结构的硅层被结合到绝缘体层以形成第三半导体结构。 切割第二硅锗层以将大部分第一半导体结构与第三半导体结构分离。 去除硅锗层以暴露随后形成晶体管的应变硅层，其后是从第一半导体结构残留的唯一层。 晶体管沿着<100>方向定向并且与第二硅的基底硅层的<100>方向成45度角。

公开(公告)号：US20070272952A1

公开(公告)日：2007-11-29

申请号：US11836844

申请日：2007-08-10

申请人： Voon-Yew Thean ,  Brian Goolsby ,  Linda McCormick ,  Bich-Yen Nguyen ,  Colita Parker ,  Mariam Sadaka ,  Victor Vartanian ,  Ted White ,  Melissa Zavala

发明人： Voon-Yew Thean ,  Brian Goolsby ,  Linda McCormick ,  Bich-Yen Nguyen ,  Colita Parker ,  Mariam Sadaka ,  Victor Vartanian ,  Ted White ,  Melissa Zavala

IPC分类号： H01L29/80

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/1203

摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

摘要翻译： 电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。 在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。 在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。 可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。 可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。 在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。