Multi-processor graphics accelerator
    1.
    发明授权
    Multi-processor graphics accelerator 有权
    多处理器图形加速器

    公开(公告)号:US06476816B1

    公开(公告)日:2002-11-05

    申请号:US09353495

    申请日:1999-07-15

    IPC分类号: G06F1516

    摘要: An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. In a similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.

    摘要翻译: 一种用于在具有多个像素的水平扫描显示装置上显示多边形的装置包括:第一和第二光栅化器,其每个处理相应的第一和第二组像素。 每组像素包括横向于显示器的水平扫描的垂直条纹。 为此,第一光栅化器具有用于接收与多边形有关的多边形数据的输入。 第一光栅化器确定要被点亮以显示多边形的第一组像素,并且还确定第一组像素的显示特性。 以类似的方式,第二光栅化器还包括用于接收与多边形有关的多边形数据的输入。 第二光栅化器类似地确定要被点亮以显示多边形的第二组像素,并且还确定第二组像素的显示特性。 第一和第二组像素没有公共像素,并且是显示装置上横向于水平扫描方向的像素的垂直条纹。

    Multisampling dithering with shuffle tables
    2.
    发明授权
    Multisampling dithering with shuffle tables 有权
    多重采样抖动与洗牌

    公开(公告)号:US06894700B2

    公开(公告)日:2005-05-17

    申请号:US10786430

    申请日:2004-02-25

    IPC分类号: G06T15/00 G09G5/00

    CPC分类号: G06T15/005 G06T11/40

    摘要: A system and method for generating random coverage masks for rendering images with transparent objects. The system uses shuffle tables for addresses of a pixel to index into a transparency table and to obtain a transparency mask, which is then ANDed with a coverage mask to obtain a new coverage mask.

    摘要翻译: 一种用于生成用于用透明对象渲染图像的随机覆盖掩码的系统和方法。 系统使用洗牌表将像素的地址索引到透明度表中并获得透明度掩码,然后将其与覆盖掩码进行“与”以获得新的覆盖掩码。

    Multi-processor graphics accelerator
    3.
    发明授权
    Multi-processor graphics accelerator 有权
    多处理器图形加速器

    公开(公告)号:US06642928B1

    公开(公告)日:2003-11-04

    申请号:US10136505

    申请日:2002-05-01

    IPC分类号: G06F1516

    摘要: An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. Similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.

    摘要翻译: 一种用于在具有多个像素的水平扫描显示装置上显示多边形的装置包括:第一和第二光栅化器,其每个处理相应的第一和第二组像素。 每组像素包括横向于显示器的水平扫描的垂直条纹。 为此,第一光栅化器具有用于接收与多边形有关的多边形数据的输入。 第一光栅化器确定要被点亮以显示多边形的第一组像素,并且还确定第一组像素的显示特性。 类似的方式,第二光栅化器还包括用于接收与多边形有关的多边形数据的输入。 第二光栅化器类似地确定要被点亮以显示多边形的第二组像素,并且还确定第二组像素的显示特性。 第一和第二组像素没有公共像素,并且是显示装置上横向于水平扫描方向的像素的垂直条纹。

    Multi-processor graphics accelerator

    公开(公告)号:US06535216B1

    公开(公告)日:2003-03-18

    申请号:US10136585

    申请日:2002-05-01

    IPC分类号: G06F1516

    摘要: An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. In a similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.

    System and method for fast gradient pixel clears in graphics rendering
    7.
    发明授权
    System and method for fast gradient pixel clears in graphics rendering 有权
    用于快速梯度像素的系统和方法在图形渲染中清除

    公开(公告)号:US07466319B1

    公开(公告)日:2008-12-16

    申请号:US10163793

    申请日:2002-06-06

    摘要: A system and method of maintaining a gradient in a plurality of pixels of a graphics display, such as a color or intensity gradient, where each pixel has an X coordinate, Y coordinate, and other pixel data that includes a fast-clear bit The pixels are filled on the display to create a gradient based upon the X or Y coordinates of the pixels, or a combination thereof, and when performing a pixel data operation, such as a read operation, the pixel data for a pixel with an activated fast-clear bit is ignored.

    摘要翻译: 维持诸如颜色或强度梯度的图形显示器的多个像素中的梯度的系统和方法,其中每个像素具有X坐标,Y坐标和包括快清晰位的其它像素数据像素 被填充在显示器上以基于像素的X或Y坐标或其组合来产生梯度,并且当执行诸如读取操作的像素数据操作时,具有激活的快速扫描的像素的像素数据, 清除位被忽略。

    Time slice processing of tessellation and geometry shaders
    9.
    发明授权
    Time slice processing of tessellation and geometry shaders 有权
    镶嵌和几何着色器的时间片处理

    公开(公告)号:US09436969B2

    公开(公告)日:2016-09-06

    申请号:US13208256

    申请日:2011-08-11

    IPC分类号: G06T1/20

    CPC分类号: G06T1/20

    摘要: One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for processing by multiple graphics pipelines. Geometric primitives that are generated in a first processing cycle are collected and redistributed more evenly and in smaller tasks to the multiple graphics pipelines for vertex processing in a second processing cycle. The smaller tasks do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second cycle are balanced and make full use of resources. Therefore, the performance of the tessellation and geometry shaders is improved.

    摘要翻译: 本发明的一个实施例提出了一种用于重新分配由镶嵌和几何着色器生成的几何图元以用于由多个图形管线进行处理的技术。 在第一个处理周期中生成的几何图元在第二个处理周期中被收集并且更均匀地并且在更小的任务中重新分布到用于顶点处理的多个图形流水线。 较小的任务不超过图形管道的资源限制,并且第二周期中的图形管道的每顶点处理工作负载平衡并充分利用资源。 因此,纹理和几何着色器的性能得到改善。

    Peer-to-peer parallel processing graphics accelerator
    10.
    发明授权
    Peer-to-peer parallel processing graphics accelerator 失效
    点对点并行处理图形加速器

    公开(公告)号:US5917502A

    公开(公告)日:1999-06-29

    申请号:US761104

    申请日:1996-12-05

    IPC分类号: G06F15/78 G06T1/20 G06F15/80

    CPC分类号: G06T1/20 G06F15/7864

    摘要: A graphics processing accelerator has a plurality of digital signal processors that each have an output, and an input in communication with a request bus. The digital signal processors are arranged in a peer-to-peer configuration to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. The graphics processing accelerator also may have a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors.

    摘要翻译: 图形处理加速器具有各自具有输出的多个数字信号处理器和与请求总线通信的输入。 数字信号处理器被布置在对等配置中,以循环的方式处理通过请求总线接收的连续的一系列图形请求中的每一个。 图形处理加速器还可以具有与每个数字信号处理器输出通信的定序器,用于排序由数字信号处理器处理的图形请求。