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1.发明授权Circuit and method of encoding and decoding digital data transmitted along optical fibers 失效对沿光纤传输的数字数据进行编码和解码的电路和方法
公开(公告)号：US5673130A
公开(公告)日：1997-09-30
申请号：US582841
申请日：1996-01-02
CPC分类号： H04B10/516 , H04L25/062 , H04L7/0008 , H04L7/0075
摘要： A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.
摘要翻译： 数据发送器（12）将并行数据作为光脉冲发送在多个光通道（14）上。 数据接收器（16）将光脉冲转换回电压电平，并将电压电平与参考电容器电压（42）进行比较。 在检测逻辑和逻辑零时，电容电压应保持适当的噪声容限的中档值。 任何长串连续的逻辑或零都会使电容器电压与数据电压相同的电平进行充放电，从而导致数据错误。 为了防止数据错误，通过反转某些位来对数据进行编码（18）以分解长序列的连续逻辑状态。 编码信息作为发送时钟通过另一个光纤信道被发送到数据接收器。 检索解码信息（20），使得编码数据可被转换回适当的逻辑状态。
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公开(公告)号：US5703506A
公开(公告)日：1997-12-30
申请号：US578726
申请日：1995-12-26
IPC分类号： H04B10/158 , H04L25/06 , H04Q9/00 , G08G1/01
CPC分类号： H04B10/697 , H04L25/062
摘要： A signal processing circuit (10) performs a sample and hold (16) of an input signal (14) and stores a maximum value of the input signal (18). A guardband signal (21) is developed that is less than the maximum value that is stored. The input signal is compared to the guardband signal to determine if the input signal is above or below the guardband signal. A threshold signal (25) is developed by taking a percentage of the maximum value that is stored. The input signal is compared to the threshold signal to regenerate the input waveform. If the input signal is below the guardband signal and above the threshold signal, the sample and hold circuit is reset to acquire a new maximum value of the input signal so that a new threshold can be used for regenerating the input signal.
摘要翻译： 信号处理电路（10）执行输入信号（14）的采样和保持（16）并存储输入信号（18）的最大值。 开发出小于存储的最大值的保护带信号（21）。 将输入信号与保护频带信号进行比较，以确定输入信号是否高于或低于保护频带信号。 通过获取存储的最大值的百分比来开发阈值信号（25）。 将输入信号与阈值信号进行比较，以重新生成输入波形。 如果输入信号低于保护带信号并且高于阈值信号，则采样和保持电路被复位以获取输入信号的新的最大值，使得可以使用新的阈值来再生输入信号。
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公开(公告)号：US6091531A
公开(公告)日：2000-07-18
申请号：US15897
申请日：1998-01-30
CPC分类号： H04B10/695 , H04B10/6932
摘要： A differential charge and dump optoelectronic receiver for baseband digital optoelectronic data links is disclosed having a preamplifier and a voltage controlled current source that defines the tail current of a differential pair functioning as a two quadrant multiplier, and using capacitors as loads on the differential pair making said differential pair an integrator. The integrator provides a full differential output, part of which is fedback to control the gain of the preamplifier. In a preferred embodiment, one integrator pair is used to recover the data from a Manchester encoded data stream. In another preferred embodiment, two pairs of integrators are used for QPSK like codes.
摘要翻译： 公开了一种用于基带数字光电数据链路的差分充电和转储光电接收器，其具有前置放大器和电压控制电流源，其限定用作二象限乘法器的差分对的尾电流，并且使用电容器作为差分对上的负载 所述差分对是积分器。 积分器提供全差分输出，其中一部分反馈控制前置放大器的增益。 在优选实施例中，使用一个积分器对来从曼彻斯特编码数据流中恢复数据。 在另一个优选实施例中，两对积分器被用于QPSK相似代码。
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公开(公告)号：US5703504A
公开(公告)日：1997-12-30
申请号：US578727
申请日：1995-12-26
CPC分类号： H03F3/08 , H03F3/3432 , H03F3/45982 , H03G3/345
摘要： A signal processing circuit (10) generates a bias signal (27) that is used for biasing a comparator (26). An input signal (14) is compared to the bias signal (27) in order to reconstruct the input signal (14) on an output of the comparator. The bias signal (27) is generated by selecting the larger of a percent of the input signal (23) or an offset signal (24) that is larger than a minimum value of the input signal.
摘要翻译： 信号处理电路（10）产生用于偏置比较器（26）的偏置信号（27）。 将输入信号（14）与偏置信号（27）进行比较，以便重建比较器的输出端上的输入信号（14）。 偏置信号（27）通过选择输入信号（23）的百分比中的较大者或大于输入信号的最小值的偏移信号（24）来产生。
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公开(公告)号：US06362644B1
公开(公告)日：2002-03-26
申请号：US09630090
申请日：2000-08-01
IPC分类号： H03K1716
CPC分类号： H03K19/01837
摘要： A receiver circuit (16) is programmable to operate with different logic family driver circuits (10). The receiver circuit has two external configuration pins (22,) 24) that are configured to provide the necessary termination for the type of logic family driver circuit used. To terminate the receiver circuit (16) for an ECL application will require first and second configuration pins (22,24) are connected to VCC—2 volts. To terminate the receiver circuit (16) for a CML application will require the first configuration pin (22) and the second configuration pin (24) are connected to VCC. LVDS termination for the receiver circuit (16) requires the first configuration pin (22) and the second configuration pin (24) are connected together. The configuration pins are external to a semiconductor package (14) housing the receiver circuit.
摘要翻译： 接收器电路（16）可编程为与不同的逻辑系列驱动电路（10）一起工作。 接收器电路具有两个外部配置引脚（22），其被配置为为所使用的逻辑系列驱动器电路的类型提供必要的端接。 为了终止用于ECL应用的接收机电路（16），将需要将第一和第二配置引脚（22,24）连接到VCC-2伏特。 为了终止用于CML应用的接收机电路（16）将需要第一配置引脚（22）和第二配置引脚（24）连接到VCC。 接收器电路（16）的LVDS终端需要第一配置引脚（22）和第二配置引脚（24）连接在一起。 配置引脚位于容纳接收器电路的半导体封装（14）的外部。
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