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公开(公告)号：US07242230B2
公开(公告)日：2007-07-10
申请号：US10787029
申请日：2004-02-25
申请人： Daniel Boyko , James F. Potts
发明人： Daniel Boyko , James F. Potts
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , G06F1/06 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held electronic devices where power management is a concern. Power can be saved by lowering the frequency of the core clock, even for short intervals of time.
摘要翻译： 一种数据处理芯片，具有灵活的定时系统和方法，用于向有用于省电的数字数据处理系统提供时钟。 锁相环产生主时钟，从中得到核心时钟和系统时钟。 每个核心和系统时钟的频率可以相对于主时钟独立控制，并且可以在无毛刺和无抖动运行的情况下随时更改。 数据处理芯片非常适合用于电力管理的手持式电子设备。 通过降低内核时钟的频率即使在短时间内也可以节省功耗。
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公开(公告)号：US07710152B1
公开(公告)日：2010-05-04
申请号：US11825541
申请日：2007-07-06
申请人： Georges El Bacha , Stuart Patterson , Daniel Boyko
发明人： Georges El Bacha , Stuart Patterson , Daniel Boyko
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113
摘要： A multistage dual logic level voltage translator for translating both high and low input logic levels to higher levels, at least one of which levels is above the maximum recommended voltage of transistors implementing the stages, includes an input stage for receiving input logic levels and an output stage including a high voltage converter having at least a pair of cross-coupled converter transistors responsive to the input stage and including a pair of clamping circuit connected one across each of the converter transistors, for providing the shifted low and high output logic levels.
摘要翻译： 一种用于将高输入逻辑电平和低输入逻辑电平转换为更高电平的多级双逻辑电平转换器，其中至少一个电平高于实施级的晶体管的最大推荐电压，包括用于接收输入逻辑电平和输出的输入级 所述高电压转换器具有响应于所述输入级的至少一对交叉耦合的转换器晶体管，并且包括在每个所述转换器晶体管之间连接的一对钳位电路，用于提供所述移位的低和高输出逻辑电平。
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公开(公告)号：US4035900A
公开(公告)日：1977-07-19
申请号：US672548
申请日：1976-03-31
申请人： Daniel Boyko , David Wallach , Mordecai Gasul
发明人： Daniel Boyko , David Wallach , Mordecai Gasul
CPC分类号： B23P19/007 , Y10T29/49906 , Y10T29/53417 , Y10T29/53478
摘要： This invention pertains to machines for installing tapped nuts, studs, or the like machine parts, whether or not having their outer surface provided with thread, knurling or similar profiles, which are to be pressed into corresponding cavities provided in a work piece, usually made of a material softer than the material of the said machine parts. The machine comprises a framework for supporting a vertically reciprocable, horizontally tractable installer head with a rotatable spindle onto which inserts are threaded one at a time for the installation thereof in suitable bores provided in the work and control means for reversing the rotation of the spindle on every installing cycle, said machine comprising insert holding means transferable between a first position, wherein the insert is held in axial alignment with respect to said spindle and a second position; means for transferring the said holding means from the first position to the second position after the threading of an insert on said spindle and means for feeding inserts to said holding means when in the second position.
摘要翻译： 本发明涉及用于安装螺纹螺纹，螺柱或类似机器部件的机器，无论其外表面是否具有螺纹，滚花或类似的型材，其被压入设置在工件中的相应的空腔中，通常制成 的材料比所述机器部件的材料软。 该机器包括用于支撑具有可旋转主轴的可垂直往复运动的水平处理的安装头的框架，在该主轴上插入件一次一个地被螺纹安装，工件和控制装置中的适当的孔中安装有插入件，用于反转主轴的旋转 每个安装周期，所述机器包括可在第一位置之间传送的插入物保持装置，其中所述插入件相对于所述主轴保持轴向对准并具有第二位置; 用于在所述主轴上的插入件穿线之后将所述保持装置从所述第一位置传送到第二位置的装置，以及当处于所述第二位置时将插入件馈入所述保持装置的装置。
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公开(公告)号：US20050184772A1
公开(公告)日：2005-08-25
申请号：US10786584
申请日：2004-02-25
申请人： James Wilson , Lew Lahr , Stuart Patterson , Daniel Boyko
发明人： James Wilson , Lew Lahr , Stuart Patterson , Daniel Boyko
摘要： An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.
摘要翻译： 具有定时电路的诸如微处理器的电子设备。 定时电路包含锁相环，其在第一间隔期间检查锁相环中的控制信号是否在最大允许值和最小允许值之间。 当锁相环中的控制信号高于最大允许值或低于最小允许值时，控制电路将第二间隔禁用锁相环。 当锁相环中的控制信号低于最大允许值并且高于最小允许值时，定时电路指示锁相环的输出稳定。
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公开(公告)号：US06956416B2
公开(公告)日：2005-10-18
申请号：US10786584
申请日：2004-02-25
申请人： James Wilson , Lew Lahr , Stuart Patterson , Daniel Boyko
发明人： James Wilson , Lew Lahr , Stuart Patterson , Daniel Boyko
摘要： An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.
摘要翻译： 具有定时电路的诸如微处理器的电子设备。 定时电路包含锁相环，其在第一间隔期间检查锁相环中的控制信号是否在最大允许值和最小允许值之间。 当锁相环中的控制信号高于最大允许值或低于最小允许值时，控制电路将第二间隔禁用锁相环。 当锁相环中的控制信号低于最大允许值并且高于最小允许值时，定时电路指示锁相环的输出稳定。
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公开(公告)号：US20050184773A1
公开(公告)日：2005-08-25
申请号：US10787029
申请日：2004-02-25
申请人： Daniel Boyko , James Potts
发明人： Daniel Boyko , James Potts
CPC分类号： H03L7/18 , G06F1/06 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held electronic devices where power management is a concern. Power can be saved by lowering the frequency of the core clock, even for short intervals of time.
摘要翻译： 一种数据处理芯片，具有灵活的定时系统和方法，用于向有用于省电的数字数据处理系统提供时钟。 锁相环产生主时钟，从中得到核心时钟和系统时钟。 每个核心和系统时钟的频率可以相对于主时钟独立控制，并且可以在无毛刺和无抖动运行的情况下随时更改。 数据处理芯片非常适合用于电力管理的手持式电子设备。 通过降低内核时钟的频率即使在短时间内也可以节省功耗。
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