公开(公告)号：US06777281B1

公开(公告)日：2004-08-17

申请号：US10214361

申请日：2002-08-08

申请人： Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

发明人： Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

IPC分类号： H01L218238

CPC分类号： H01L29/6659 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823814 ,  H01L29/6656

摘要： A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semi conductor substrate including at least one dopant species-containing region extending to a surface of the substrate; (b) forming a thin liner oxide layer on the surface of the substrate; and (c) incorporating in the thin line oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：（a）提供半导体衬底，其包括至少一个延伸到衬底表面的含掺杂物种的区域;（b）在衬底的表面上形成薄的衬里氧化物层 基材; 和（c）在细线氧化物层中并入至少一种物质，其至少一种物质，其基本上防止或至少减少其中从至少一种含掺杂物种的区域移动而引起的掺杂物质的偏析。

公开(公告)号：US06589847B1

公开(公告)日：2003-07-08

申请号：US09631557

申请日：2000-08-03

申请人： Daniel Kadosh ,  Scott D. Luning ,  Derick J. Wristers

发明人： Daniel Kadosh ,  Scott D. Luning ,  Derick J. Wristers

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/6656

摘要： The present invention is directed to a method of forming halo implant regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, the substrate being doped with a first type of dopant material, and forming halo implant regions in the substrate adjacent the gate electrode by performing at least the following steps: performing a first angled implant process using a dopant material that is of a type opposite to the first type of dopant material and performing a second angled implant using a dopant material that is of the same type as the first type of dopant material. The method concludes with performing at least one additional implantation process to further form source/drain regions for the device.

摘要翻译： 本发明涉及一种在半导体器件中形成卤素注入区的方法。 在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，该衬底被掺杂有第一种类型的掺杂剂材料，以及通过至少执行以下步骤在邻近栅极的衬底中形成卤素注入区域：执行 使用与第一类型的掺杂剂材料相反的类型的掺杂剂材料并使用与第一类型的掺杂剂材料具有相同类型的掺杂剂材料来执行第二成角度的注入的第一成角度注入工艺。 该方法的结论是执行至少一个额外的注入工艺以进一步形成器件的源极/漏极区域。

公开(公告)号：US06506642B1

公开(公告)日：2003-01-14

申请号：US10020931

申请日：2001-12-19

申请人： Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

发明人： Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

IPC分类号： H01L218238

CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656

摘要： Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.

摘要翻译： 亚微米尺寸的MOS和/或CMOS晶体管使用简化的可移除侧壁间隔物技术制造，使得能够有效地定制各个晶体管以优化它们各自的功能。 实施例包括在晶体管的多个栅极电极的侧表面上形成具有第一厚度的第一侧壁间隔物，从某些晶体管的栅电极选择性地去除第一侧壁间隔物，然后在剩余的第一侧壁间隔物上沉积第二侧壁间隔物， 在栅电极的已经被去除了第一侧壁间隔物的侧表面上。 实施例能够单独定制n型和p型MOS晶体管以及具有不同功能的单独n型或p型MOS晶体管，例如不同的驱动电流和电压泄漏要求。

公开(公告)号：US06949436B2

公开(公告)日：2005-09-27

申请号：US10824428

申请日：2004-04-15

申请人： James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

发明人： James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

摘要： Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner under a gate electrode sidewall spacer. Embodiments include depositing a conformal oxide layer by decoupled plasma deposition, depositing a conformal nitride layer by decoupled plasma deposition, depositing a spacer layer and then etching.

摘要翻译： 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物下形成复合氧化物/氮化物衬垫来制造。 实施例包括通过解耦等离子体沉积沉积保形氧化物层，通过去耦等离子体沉积沉积共形氮化物层，沉积间隔层然后蚀刻。

公开(公告)号：US07315765B1

公开(公告)日：2008-01-01

申请号：US11192691

申请日：2005-07-29

申请人： Alan Grosvenor Ranft ,  Daniel Kadosh

发明人： Alan Grosvenor Ranft ,  Daniel Kadosh

IPC分类号： G06F19/00

CPC分类号： G05B19/404 ,  G05B19/4187 ,  G05B2219/32297 ,  G05B2219/45031 ,  Y02P90/205

摘要： A method, apparatus, and a system for determining a control thread based upon a process result are provided. At least one post-process parameter is received. The post parameter relates to a first workpiece upon which a plurality of processes have been performed by a plurality of processing tools. A combination of at least a portion of the plurality of processing tools is selected based upon the post-process parameter.

摘要翻译： 提供了一种基于处理结果来确定控制线程的方法，装置和系统。 接收至少一个后处理参数。 后参数涉及由多个处理工具执行多个处理的第一工件。 基于后处理参数来选择多个处理工具的至少一部分的组合。

公开(公告)号：US07248939B1

公开(公告)日：2007-07-24

申请号：US11035276

申请日：2005-01-13

申请人： Kevin Andrew Chamness ,  Daniel Kadosh ,  Gregory A. Cherry ,  Jason Williams

发明人： Kevin Andrew Chamness ,  Daniel Kadosh ,  Gregory A. Cherry ,  Jason Williams

IPC分类号： G06F19/00

CPC分类号： H01L21/67288 ,  H01L21/67276

摘要： The present invention provides a method and apparatus for multivariate fault identification and classification. The method includes accessing data indicative of a plurality of physical parameters associated with a plurality of processed semiconductor wafers and providing at least one summary report including information indicative of at least one univariate representation of the accessed data and at least one multivariate representation of the accessed data.

摘要翻译： 本发明提供了一种用于多变量故障识别和分类的方法和装置。 该方法包括访问指示与多个处理的半导体晶片相关联的多个物理参数的数据，并且提供包括指示所访问数据的至少一个单变量表示的信息的至少一个概要报告和所访问数据的至少一个多变量表示 。

公开(公告)号：US06403979B1

公开(公告)日：2002-06-11

申请号：US09780834

申请日：2001-02-09

申请人： Daniel Kadosh ,  Jon D. Cheek

发明人： Daniel Kadosh ,  Jon D. Cheek

IPC分类号： H01L2358

CPC分类号： H01L22/34

摘要： A test structure for use in determining an effective channel length of a transistor is disclosed herein. The test structure comprises a first resistor comprised of a first doped region formed in a semiconducting substrate between a first pair of spaced-apart structures positioned above the substrate, the first resistor having a first width defined by the spacing between the first pair of structures, a second resistor comprised of a second doped region formed in the substrate between a second pair of spaced-apart structures positioned above the substrate, the second resistor having a second width defined by the spacing between the second pair of structures, the second width being greater than the first width, and a plurality of conductive contacts electrically coupled to each of the first and second doped regions. The method disclosed herein comprises determining the extent of lateral encroachment of the doped regions under the structures based upon the following formula: &Dgr;w=(R1W1 −R2W2)/(R1−R2). The effective channel length of the transistor may be determined by subtracting the &Dgr;w value from the length of the gate electrode.

摘要翻译： 本文公开了用于确定晶体管的有效沟道长度的测试结构。 测试结构包括第一电阻器，该第一电阻器由形成在半导体衬底中的第一掺杂区域构成，位于衬底上方的第一对隔开的结构之间，第一电阻器具有由第一对结构之间的间隔限定的第一宽度， 第二电阻器，包括形成在衬底中的位于衬底上方的第二对隔开的结构之间的第二掺杂区域，第二电阻器具有由第二对结构之间的间隔限定的第二宽度，第二宽度更大 并且多个导电触点电耦合到第一和第二掺杂区域中的每一个。 本文公开的方法包括基于以下公式确定结构下的掺杂区域的横向侵入的程度：DELTAw =（R1W1-R2W2）/（R1-R2）。 可以通过从栅电极的长度减去DELTAw值来确定晶体管的有效沟道长度。

公开(公告)号：US06232637B1

公开(公告)日：2001-05-15

申请号：US09249954

申请日：1999-02-12

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L31036

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure. Select portions of the primary and secondary interlevel dielectrics are then removed to expose one of the junctions and a portion of the doped polysilicon structure arranged proximate this junction. An interconnect is formed contiguously between the junction and the polysilicon structure by depositing a conductive material within the removed portions.

摘要翻译： 提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构。 升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。 升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。 提供晶体管，其包括在一对结之间间隔开的栅极导体。 在晶体管两端沉积初级层间电介质。 在初级层间电介质的上表面的选择部分内形成多晶硅结构。 多晶硅结构是距离晶体管的上方和横向距离之间的间隔距离。 将掺杂剂注入到多晶硅结构中。 次级层间电介质沉积在初级层间电介质和掺杂多晶硅结构之间。 选择部分初级和次级层间电介质然后被去除以暴露出一个结点，并且掺杂多晶硅结构的一部分布置在该结附近。 通过在去除的部分内沉积导电材料，在结和多晶硅结构之间连续地形成互连。

公开(公告)号：US06218251B1

公开(公告)日：2001-04-17

申请号：US09187894

申请日：1998-11-06

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21336

CPC分类号： H01L29/66598 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/7835

摘要： In an IGFET device having at least one source/drain region with a lightly-doped sub-region proximate a channel region, the source/drain regions are formed by first implanting ions with parameters to form lightly-doped source/drain regions. A high density plasma deposition provides at least one spacer having preselected characteristics. As a result of the spacer characteristics, an ion implantation with parameters to form normally-doped source/drain regions is shadowed by the spacer. A portion of the source/drain region shadowed by the spacer results in a lightly-doped source/drain sub-region proximate the channel region. According to a second embodiment of the invention, the ion implantation resulting in the lightly-doped source/drain regions is eliminated. Instead, the spacer(s) formed by the high density plasma deposition and subsequent etching process only partially shadows the ion implantation that would otherwise result in normal doping of the source/drain regions. The parameters of the spacer(s) resulting from the high density plasma deposition and subsequent etching process result in a lightly-doped source/drain sub-region proximate the channel region. The shadowing of the spacer decreases with distance from the gate structure and results in a normal doping level for the portion of the source/drain terminal not shadowed by the spacer.

摘要翻译： 在具有至少一个具有靠近沟道区的轻掺杂子区域的源极/漏极区域的IGFET器件中，通过首先用参数注入离子以形成轻掺杂的源极/漏极区域来形成源极/漏极区域。 高密度等离子体沉积提供至少一个具有预选特性的间隔物。 作为间隔物特性的结果，具有形成常态掺杂源极/漏极区域的参数的离子注入被间隔物遮蔽。 由间隔物遮蔽的源极/漏极区域的一部分导致靠近沟道区域的轻掺杂源极/漏极子区域。 根据本发明的第二实施例，消除了导致轻掺杂源/漏区的离子注入。 替代地，通过高密度等离子体沉积和随后的蚀刻工艺形成的间隔物仅部分地影响否则将导致源/漏区的正常掺杂的离子注入。 由高密度等离子体沉积和随后的蚀刻工艺产生的间隔物的参数导致靠近沟道区的轻掺杂的源极/漏极子区域。 间隔物的阴影随着与栅极结构的距离而减小，并且导致源极/漏极端子的未被间隔物遮蔽的部分的正常掺杂水平。

公开(公告)号：US06172381B2

公开(公告)日：2001-01-09

申请号：US09219146

申请日：1998-12-22

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L2702

CPC分类号： H01L21/76897 ,  H01L21/76838 ,  H01L21/8221 ,  H01L23/5226 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer. The second transistor has a pair of implant regions spaced from each other by a gate conductor and a pair of oxide spacers arranged on opposed sidewall surfaces of the gate conductor. Part of the polysilicon layer is removed such that polysilicon only extends under the gate conductor and terminates a pre-defined distance from each of the pair of oxide spacers. A pair of junctions remain for the second transistor that are defined between an etched lateral edge and an oxide spacer. A second interlevel dielectric may be deposited across the second transistor and exposed areas of the primary interlevel dielectric to isolate the transistor from other active devices.

摘要翻译： 提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构并将其与位于同一高架平面中的另一多晶硅结构隔离。 升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。 升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。 提供了第一晶体管，其设置在硅基衬底上并且位于硅基衬底内。 在晶体管和衬底两端沉积初级层间电介质。 然后可以将多晶硅沉积在初级层间电介质上并使用离子注入进行掺杂。 可以在多晶硅层的一部分上形成第二晶体管。 第二晶体管具有通过栅极导体和布置在栅极导体的相对的侧壁表面上的一对氧化物隔离物彼此隔开的一对注入区域。 去除多晶硅层的一部分，使得多晶硅仅在栅极导体下方延伸并且终止与一对氧化物间隔物中的每一个的预定距离。 在蚀刻的侧边缘和氧化物间隔物之间​​限定的第二晶体管保留一对结。 可以跨越第二晶体管和初级层间电介质的暴露区域沉积第二层间电介质以将晶体管与其它有源器件隔离。