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    Method and apparatus for multivariate fault detection and classification
    1.
    发明授权
    Method and apparatus for multivariate fault detection and classification 有权
    多变量故障检测和分类方法与装置

    公开(公告)号：US07248939B1

    公开(公告)日：2007-07-24

    申请号：US11035276

    申请日：2005-01-13

    申请人： Kevin Andrew Chamness ,  Daniel Kadosh ,  Gregory A. Cherry ,  Jason Williams

    发明人： Kevin Andrew Chamness ,  Daniel Kadosh ,  Gregory A. Cherry ,  Jason Williams

    IPC分类号： G06F19/00

    CPC分类号： H01L21/67288 ,  H01L21/67276

    摘要： The present invention provides a method and apparatus for multivariate fault identification and classification. The method includes accessing data indicative of a plurality of physical parameters associated with a plurality of processed semiconductor wafers and providing at least one summary report including information indicative of at least one univariate representation of the accessed data and at least one multivariate representation of the accessed data.

    摘要翻译： 本发明提供了一种用于多变量故障识别和分类的方法和装置。 该方法包括访问指示与多个处理的半导体晶片相关联的多个物理参数的数据，并且提供包括指示所访问数据的至少一个单变量表示的信息的至少一个概要报告和所访问数据的至少一个多变量表示 。

    DETERMINING DIE PERFORMANCE BY INCORPORATING NEIGHBORING DIE PERFORMANCE METRICS
    3.
    发明申请
    DETERMINING DIE PERFORMANCE BY INCORPORATING NEIGHBORING DIE PERFORMANCE METRICS 有权
    确定相邻性能性能指标的性能

    公开(公告)号：US20080244348A1

    公开(公告)日：2008-10-02

    申请号：US11692989

    申请日：2007-03-29

    申请人： Daniel Kadosh ,  Gregory A. Cherry ,  Carl Bowen ,  Luis De La Fuente ,  Rajesh Vijayaraghavan

    发明人： Daniel Kadosh ,  Gregory A. Cherry ,  Carl Bowen ,  Luis De La Fuente ,  Rajesh Vijayaraghavan

    IPC分类号： G06F11/00

    CPC分类号： G01R31/287

    摘要： A method includes receiving a first set of parameters associated with a plurality of die. A first die performance metric associated with a selected die is determined based on the first set of parameters. At least one neighborhood die performance metric associated with a set comprised of a plurality of die that neighbor the selected die is determined based on the first set of parameters. A second die performance metric is determined for the selected die based on the first die performance metric and the neighborhood die performance metric.

    摘要翻译： 一种方法包括接收与多个管芯相关联的第一组参数。 基于第一组参数来确定与所选择的管芯相关联的第一管芯性能度量。 基于第一组参数来确定与由与选定的管芯相邻的多个管芯组成的组相关联的至少一个邻近管芯性能度量。 基于第一管芯性能度量和邻近管芯性能度量，为所选择的管芯确定第二管芯性能度量。

    Method and apparatus for detecting faults using principal component analysis parameter groupings
    4.
    发明授权
    Method and apparatus for detecting faults using principal component analysis parameter groupings 失效
    使用主成分分析参数分组检测故障的方法和装置

    公开(公告)号：US07198964B1

    公开(公告)日：2007-04-03

    申请号：US10770681

    申请日：2004-02-03

    申请人： Gregory A. Cherry ,  Daniel Kadosh

    发明人： Gregory A. Cherry ,  Daniel Kadosh

    IPC分类号： H01L21/66

    CPC分类号： H01L22/20 ,  G05B19/41875 ,  G05B2219/37224 ,  H01L22/14 ,  Y02P90/22

    摘要： A method for identifying faults in a semiconductor fabrication process includes storing measurements for a plurality of parameters of a wafer in the semiconductor fabrication process. A first subset of the parameters is selected. The subset is associated with a feature formed on the wafer. A principal component analysis model is applied to the first subset to generate a performance metric. A fault condition with the wafer is identified based on the performance metric. A system includes a data store and a fault monitor. The data store is adapted to store measurements for a plurality of parameters of a wafer in a semiconductor fabrication process. The fault monitor is adapted to select a first subset of the parameters, the subset being associated with a feature formed on the wafer, apply a principal component analysis model to the first subset to generate a performance metric, and identify a fault condition with the wafer based on the performance metric.

    摘要翻译： 用于识别半导体制造工艺中的故障的方法包括在半导体制造工艺中存储晶片的多个参数的测量。 选择参数的第一个子集。 该子集与形成在晶片上的特征相关联。 主成分分析模型应用于第一子集以生成性能指标。 基于性能度量来识别晶片的故障状况。 系统包括数据存储和故障监视器。 数据存储器适于在半导体制造过程中存储晶片的多个参数的测量。 所述故障监视器适于选择所述参数的第一子集，所述子集与形成在所述晶片上的特征相关联，将主分量分析模型应用于所述第一子集以产生性能度量，并且识别所述晶片的故障状况 基于性能指标。

    Automated control thread determination based upon post-process consideration
    6.
    发明授权
    Automated control thread determination based upon post-process consideration 有权
    基于后处理考虑的自动控制线程确定

    公开(公告)号：US07315765B1

    公开(公告)日：2008-01-01

    申请号：US11192691

    申请日：2005-07-29

    申请人： Alan Grosvenor Ranft ,  Daniel Kadosh

    发明人： Alan Grosvenor Ranft ,  Daniel Kadosh

    IPC分类号： G06F19/00

    CPC分类号： G05B19/404 ,  G05B19/4187 ,  G05B2219/32297 ,  G05B2219/45031 ,  Y02P90/205

    摘要： A method, apparatus, and a system for determining a control thread based upon a process result are provided. At least one post-process parameter is received. The post parameter relates to a first workpiece upon which a plurality of processes have been performed by a plurality of processing tools. A combination of at least a portion of the plurality of processing tools is selected based upon the post-process parameter.

    摘要翻译： 提供了一种基于处理结果来确定控制线程的方法，装置和系统。 接收至少一个后处理参数。 后参数涉及由多个处理工具执行多个处理的第一工件。 基于后处理参数来选择多个处理工具的至少一部分的组合。

    Test structure for measuring effective channel length of a transistor
    7.
    发明授权
    Test structure for measuring effective channel length of a transistor 失效
    用于测量晶体管有效沟道长度的测试结构

    公开(公告)号：US06403979B1

    公开(公告)日：2002-06-11

    申请号：US09780834

    申请日：2001-02-09

    申请人： Daniel Kadosh ,  Jon D. Cheek

    发明人： Daniel Kadosh ,  Jon D. Cheek

    IPC分类号： H01L2358

    CPC分类号： H01L22/34

    摘要： A test structure for use in determining an effective channel length of a transistor is disclosed herein. The test structure comprises a first resistor comprised of a first doped region formed in a semiconducting substrate between a first pair of spaced-apart structures positioned above the substrate, the first resistor having a first width defined by the spacing between the first pair of structures, a second resistor comprised of a second doped region formed in the substrate between a second pair of spaced-apart structures positioned above the substrate, the second resistor having a second width defined by the spacing between the second pair of structures, the second width being greater than the first width, and a plurality of conductive contacts electrically coupled to each of the first and second doped regions. The method disclosed herein comprises determining the extent of lateral encroachment of the doped regions under the structures based upon the following formula: &Dgr;w=(R1W1 −R2W2)/(R1−R2). The effective channel length of the transistor may be determined by subtracting the &Dgr;w value from the length of the gate electrode.

    摘要翻译： 本文公开了用于确定晶体管的有效沟道长度的测试结构。 测试结构包括第一电阻器，该第一电阻器由形成在半导体衬底中的第一掺杂区域构成，位于衬底上方的第一对隔开的结构之间，第一电阻器具有由第一对结构之间的间隔限定的第一宽度， 第二电阻器，包括形成在衬底中的位于衬底上方的第二对隔开的结构之间的第二掺杂区域，第二电阻器具有由第二对结构之间的间隔限定的第二宽度，第二宽度更大 并且多个导电触点电耦合到第一和第二掺杂区域中的每一个。 本文公开的方法包括基于以下公式确定结构下的掺杂区域的横向侵入的程度：DELTAw =（R1W1-R2W2）/（R1-R2）。 可以通过从栅电极的长度减去DELTAw值来确定晶体管的有效沟道长度。

    Semiconductor fabrication having multi-level transistors and high density interconnect therebetween
    8.
    发明授权
    Semiconductor fabrication having multi-level transistors and high density interconnect therebetween 有权
    具有多电平晶体管和其间的高密度互连的半导体制造

    公开(公告)号：US06232637B1

    公开(公告)日：2001-05-15

    申请号：US09249954

    申请日：1999-02-12

    申请人： Mark I. Gardner ,  Daniel Kadosh

    发明人： Mark I. Gardner ,  Daniel Kadosh

    IPC分类号： H01L31036

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure. Select portions of the primary and secondary interlevel dielectrics are then removed to expose one of the junctions and a portion of the doped polysilicon structure arranged proximate this junction. An interconnect is formed contiguously between the junction and the polysilicon structure by depositing a conductive material within the removed portions.

    摘要翻译： 提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构。 升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。 升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。 提供晶体管，其包括在一对结之间间隔开的栅极导体。 在晶体管两端沉积初级层间电介质。 在初级层间电介质的上表面的选择部分内形成多晶硅结构。 多晶硅结构是距离晶体管的上方和横向距离之间的间隔距离。 将掺杂剂注入到多晶硅结构中。 次级层间电介质沉积在初级层间电介质和掺杂多晶硅结构之间。 选择部分初级和次级层间电介质然后被去除以暴露出一个结点，并且掺杂多晶硅结构的一部分布置在该结附近。 通过在去除的部分内沉积导电材料，在结和多晶硅结构之间连续地形成互连。

    Asymmetrical IGFET devices with spacers formed by HDP techniques
    9.
    发明授权
    Asymmetrical IGFET devices with spacers formed by HDP techniques 有权
    通过HDP技术形成间隔物的非对称IGFET器件

    公开(公告)号：US06218251B1

    公开(公告)日：2001-04-17

    申请号：US09187894

    申请日：1998-11-06

    申请人： Daniel Kadosh ,  Mark I. Gardner

    发明人： Daniel Kadosh ,  Mark I. Gardner

    IPC分类号： H01L21336

    CPC分类号： H01L29/66598 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/7835

    摘要： In an IGFET device having at least one source/drain region with a lightly-doped sub-region proximate a channel region, the source/drain regions are formed by first implanting ions with parameters to form lightly-doped source/drain regions. A high density plasma deposition provides at least one spacer having preselected characteristics. As a result of the spacer characteristics, an ion implantation with parameters to form normally-doped source/drain regions is shadowed by the spacer. A portion of the source/drain region shadowed by the spacer results in a lightly-doped source/drain sub-region proximate the channel region. According to a second embodiment of the invention, the ion implantation resulting in the lightly-doped source/drain regions is eliminated. Instead, the spacer(s) formed by the high density plasma deposition and subsequent etching process only partially shadows the ion implantation that would otherwise result in normal doping of the source/drain regions. The parameters of the spacer(s) resulting from the high density plasma deposition and subsequent etching process result in a lightly-doped source/drain sub-region proximate the channel region. The shadowing of the spacer decreases with distance from the gate structure and results in a normal doping level for the portion of the source/drain terminal not shadowed by the spacer.

    摘要翻译： 在具有至少一个具有靠近沟道区的轻掺杂子区域的源极/漏极区域的IGFET器件中，通过首先用参数注入离子以形成轻掺杂的源极/漏极区域来形成源极/漏极区域。 高密度等离子体沉积提供至少一个具有预选特性的间隔物。 作为间隔物特性的结果，具有形成常态掺杂源极/漏极区域的参数的离子注入被间隔物遮蔽。 由间隔物遮蔽的源极/漏极区域的一部分导致靠近沟道区域的轻掺杂源极/漏极子区域。 根据本发明的第二实施例，消除了导致轻掺杂源/漏区的离子注入。 替代地，通过高密度等离子体沉积和随后的蚀刻工艺形成的间隔物仅部分地影响否则将导致源/漏区的正常掺杂的离子注入。 由高密度等离子体沉积和随后的蚀刻工艺产生的间隔物的参数导致靠近沟道区的轻掺杂的源极/漏极子区域。 间隔物的阴影随着与栅极结构的距离而减小，并且导致源极/漏极端子的未被间隔物遮蔽的部分的正常掺杂水平。

    Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall
    10.
    发明授权
    Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall 有权
    源极/漏极结区域在侧壁间隔物和蚀刻的侧壁之间自对准

    公开(公告)号：US06172381B2

    公开(公告)日：2001-01-09

    申请号：US09219146

    申请日：1998-12-22

    申请人： Mark I. Gardner ,  Daniel Kadosh

    发明人： Mark I. Gardner ,  Daniel Kadosh

    IPC分类号： H01L2702

    CPC分类号： H01L21/76897 ,  H01L21/76838 ,  H01L21/8221 ,  H01L23/5226 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer. The second transistor has a pair of implant regions spaced from each other by a gate conductor and a pair of oxide spacers arranged on opposed sidewall surfaces of the gate conductor. Part of the polysilicon layer is removed such that polysilicon only extends under the gate conductor and terminates a pre-defined distance from each of the pair of oxide spacers. A pair of junctions remain for the second transistor that are defined between an etched lateral edge and an oxide spacer. A second interlevel dielectric may be deposited across the second transistor and exposed areas of the primary interlevel dielectric to isolate the transistor from other active devices.

    摘要翻译： 提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构并将其与位于同一高架平面中的另一多晶硅结构隔离。 升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。 升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。 提供了第一晶体管，其设置在硅基衬底上并且位于硅基衬底内。 在晶体管和衬底两端沉积初级层间电介质。 然后可以将多晶硅沉积在初级层间电介质上并使用离子注入进行掺杂。 可以在多晶硅层的一部分上形成第二晶体管。 第二晶体管具有通过栅极导体和布置在栅极导体的相对的侧壁表面上的一对氧化物隔离物彼此隔开的一对注入区域。 去除多晶硅层的一部分，使得多晶硅仅在栅极导体下方延伸并且终止与一对氧化物间隔物中的每一个的预定距离。 在蚀刻的侧边缘和氧化物间隔物之间​​限定的第二晶体管保留一对结。 可以跨越第二晶体管和初级层间电介质的暴露区域沉积第二层间电介质以将晶体管与其它有源器件隔离。