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公开(公告)号：US20090203347A1
公开(公告)日：2009-08-13
申请号：US12028720
申请日：2008-02-08
摘要： A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.
摘要翻译： 基带接收机（202）中的平衡混频器电路（300,400,500,600,700和800）包括振荡器电路（212），混频器（214和215），数模转换器（258和 259）和数字信号处理器（250）。 混频器包括CMOS器件（301,302,303和304）。 响应于来自混频器的差分输出，数字信号处理器控制数模转换器以输出混频器的至少一个CMOS器件的栅极的偏置电压，以补偿混频器的差分输出的不平衡 这可能是由混频器的两个或更多个CMOS器件之间的失配引起的或由于其他原因引起的，以便增加混频器的二阶截取点。
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公开(公告)号：US08676145B2
公开(公告)日：2014-03-18
申请号：US13095544
申请日：2011-04-27
摘要： A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.
摘要翻译： 基带接收机（202）中的平衡混频器电路（300,400,500,600,700和800）包括振荡器电路（212），混频器（214和215），数模转换器（258和 259）和数字信号处理器（250）。 混频器包括CMOS器件（301,302,303和304）。 响应于来自混频器的差分输出，数字信号处理器控制数模转换器以输出混频器的至少一个CMOS器件的栅极的偏置电压，以补偿混频器的差分输出的不平衡 这可能是由混频器的两个或更多个CMOS器件之间的失配引起的或由于其他原因引起的，以便增加混频器的二阶截取点。
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公开(公告)号：US08010074B2
公开(公告)日：2011-08-30
申请号：US12028720
申请日：2008-02-08
摘要： A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.
摘要翻译： 基带接收机（202）中的平衡混频器电路（300,400,500,600,700和800）包括振荡器电路（212），混频器（214和215），数模转换器（258和 259）和数字信号处理器（250）。 混频器包括CMOS器件（301,302,303和304）。 响应于来自混频器的差分输出，数字信号处理器控制数模转换器以输出混频器的至少一个CMOS器件的栅极的偏置电压，以补偿混频器的差分输出的不平衡 这可能是由混频器的两个或更多个CMOS器件之间的失配引起的或由于其他原因引起的，以便增加混频器的二阶截取点。
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4.发明授权公开(公告)号：US08126422B2
公开(公告)日：2012-02-28
申请号：US12103452
申请日：2008-04-15
IPC分类号： H04B1/16
CPC分类号： H04B1/30
摘要： A receiver (300) comprises an antenna input (301), a filter (302), a voltage-to-current converter (303), a down frequency conversion mixer (304), and a current-to-voltage converter (305). The antenna input operably couples to an antenna. The filter has a filter input that operably couples to the antenna input and can further have a filter output. The voltage-to-current converter has an input that is operably coupled to the filter output and can further have a voltage-to-current converter output. The down frequency conversion mixer has a mixer input that is operably coupled to the voltage-to-current converter output and can further have a mixer output. And the current-to-voltage converter has an input that is operably coupled to the mixer output and can further have a current-to-voltage converter output. By one approach, this current-to-voltage converter comprises an amplifier having a current gain of substantially unity or less.
摘要翻译： 接收器（300）包括天线输入（301），滤波器（302），电压 - 电流转换器（303），下变频混频器（304）和电流 - 电压转换器（305） 。 天线输入可操作地耦合到天线。 滤波器具有可操作地耦合到天线输入并且可以进一步具有滤波器输出的滤波器输入。 电压 - 电流转换器具有可操作地耦合到滤波器输出的输入，并且还可以具有电压 - 电流转换器输出。 下变频混频器具有可操作地耦合到电压 - 电流转换器输出的混频器输入，并且还可以具有混频器输出。 并且电流 - 电压转换器具有可操作地耦合到混频器输出的输入，并且还可以具有电流 - 电压转换器输出。 通过一种方法，该电流 - 电压转换器包括具有基本上一致或更小的电流增益的放大器。
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公开(公告)号：US6018750A
公开(公告)日：2000-01-25
申请号：US511667
申请日：1995-08-07
CPC分类号： G06K9/0051 , G06F17/18 , H03H17/0263
摘要： A fast and efficient median search method and filter searches a dynamically changing time-ordered list of data samples for a data sample representing the arithmetic median of the list. Embodiments include a method to reduce the number of memory access operations to 2N and a method to reduce the number of memory access operations to N, where N is the number of data samples searched. The described approach includes providing a circular list of N data samples including an incoming data sample replacing an outgoing data sample, and a median data sample. Then, updating the median data sample dependent on magnitudes of the incoming data sample, the median data sample, and the outgoing data sample.
摘要翻译： 快速有效的中值搜索方法和过滤器搜索表示列表的算术中值的数据样本的动态变化的时间序列数据样本列表。 实施例包括将存储器访问操作数减少到2N的方法以及将存储器访问操作数减少到N的方法，其中N是搜索的数据样本的数量。 所描述的方法包括提供N个数据样本的循环列表，包括取代输出数据样本的输入数据样本和中值数据样本。 然后，根据输入数据样本的幅度，中值数据样本和输出数据样本更新中值数据样本。
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6.发明授权Communication device with a frequency compensating synthesizer and method of providing same 失效具有频率补偿合成器的通信装置及其提供方法
公开(公告)号：US5856766A
公开(公告)日：1999-01-05
申请号：US885003
申请日：1997-06-30
CPC分类号： H03L7/23 , H03L1/026 , H03L7/197 , H03L7/1974 , H04B1/403
摘要： A communication device including a plurality of frequency synthesizers (24, 28, 30). At least one of the frequency synthesizers (24) is driven with a reference frequency from a crystal oscillator (58). The at least one frequency synthesizer (24) includes a phase locked loop with a fractional-N divider (48) which is programmed by a control circuit (64) to vary as a function of temperature compensation, frequency compensation, and a frequency multiplication factor. The output (46) of the at least one frequency synthesizer (24) is used to provide a compensated reference frequency input for the remaining frequency synthesizers (28, 30). The radio provides all the frequency synthesizers (24, 28, 30) with temperature and frequency compensation using a reference frequency from a crystal oscillator (58) and only one high resolution frequency compensating synthesizer (24).
摘要翻译： 一种包括多个频率合成器（24,28,30）的通信装置。 频率合成器（24）中的至少一个以来自晶体振荡器（58）的参考频率驱动。 所述至少一个频率合成器（24）包括具有分数N分频器（48）的锁相环，该分频器由控制电路（64）编程以根据温度补偿，频率补偿和频率倍增因子 。 所述至少一个频率合成器（24）的输出（46）用于为剩余频率合成器（28,30）提供经补偿的参考频率输入。 无线电设备使用来自晶体振荡器（58）和仅一个高分辨率频率补偿合成器（24）的参考频率来提供所有频率合成器（24,28,30）的温度和频率补偿。
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公开(公告)号：US5530403A
公开(公告)日：1996-06-25
申请号：US432646
申请日：1995-05-03
IPC分类号： H03F3/45
CPC分类号： H03F3/45076
摘要： A low-voltage differential amplifier (10) includes a circuit (12) having a differential pair (14) and loads (22 and 24). The first load (22) can include a first embedded differential amplifier (30) and an output transistor (32) and the second load (24) can include a second embedded differential amplifier (36) and an output transistor (38). The differential amplifier (10) can provide a wide-voltage operable range. The differential amplifier (10) is particularly useful in connection with low-voltage temperature compensated crystal oscillators.
摘要翻译： 低压差分放大器（10）包括具有差分对（14）和负载（22和24）的电路（12）。 第一负载（22）可以包括第一嵌入式差分放大器（30）和输出晶体管（32），第二负载（24）可以包括第二嵌入式差分放大器（36）和输出晶体管（38）。 差分放大器（10）可以提供宽电压可操作的范围。 差分放大器（10）在低压温度补偿晶体振荡器方面特别有用。
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公开(公告)号：US4982108A
公开(公告)日：1991-01-01
申请号：US227589
申请日：1988-08-02
IPC分类号： H03K12/00 , H03K19/0185
CPC分类号： H03K19/018521 , H03K12/00
摘要： A low current CMOS translator arrangement is disclosed that utilizes a low current inverting stage, having a peak current requirement, fed by a constant current source at a supply node that also has a capacitor coupled to it. This low current inverter is useful for a number of applications, including generating a sinusoidal signal when it is coupled to a crystal. When one or more are cascaded and coupled to a square wave input signal, the arrangement becomes a low current translator that level-shifts, or translates, the input signal having a first voltage range to a translated square wave output signal having a second voltage range. In another embodiment called a low current squaring translator, a squaring stage is coupled between the low current inverter and a low current translator that includes one or more inverting stages. This arrangement is able to achieve an output signal that maintains a precise duty cycle with low noise at a very low current.
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公开(公告)号：US4710724A
公开(公告)日：1987-12-01
申请号：US847361
申请日：1986-04-02
CPC分类号： H03K17/302
摘要： A differential input circuit for a switched capacitor CMOS voltage comparator is provided which minimizes offset voltages by configuring the load devices to utilize a single switched capacitor biasing network initialized from internally-generated bias voltages, while configuring the initialization switches for the differential input devices to also utilize internally-generated bias voltages such that the offset voltages are stored on the input capacitors. The power supply rejection performance of the voltage comparator is also optimized by connecting parallel load devices of opposite switching topology such that the same input impedance is seen at both load terminals.
摘要翻译： 提供了一种用于开关电容器CMOS电压比较器的差分输入电路，其通过将负载装置配置为利用从内部产生的偏置电压初始化的单个开关电容器偏置网络来最小化偏移电压，同时将差分输入装置的初始化开关配置为 利用内部产生的偏置电压，使得偏移电压存储在输入电容器上。 电压比较器的电源抑制性能也通过连接相反开关拓扑的并联负载器件进行优化，从而在两个负载端子都可以看到相同的输入阻抗。
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公开(公告)号：US4398265A
公开(公告)日：1983-08-09
申请号：US187305
申请日：1980-09-15
申请人： Larry C. Puhl , Lawrence E. Connell
发明人： Larry C. Puhl , Lawrence E. Connell
CPC分类号： G06F3/0227
摘要： A unique interface adapter is coupled to a microprocessor by a three-wire self-clocking serial data bus for accommodating a twenty-key keyboard and an eight-digit display. The interface adapter includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from the data signal transmitted on two forward signal lines of the serial data bus. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether a control register or display register is to be loaded in response to the read/write signal with the data portion of the data signal. The control register signals activate four status indicating LED's, apply power to the display, select between a ten or sixteen digit display, enable an audio tone generator and reset a status bit flip-flop. The display register receives two BCD digits which are stored in a display memory. The keys of the keyboard are scanned at the same time digits read-out from the display memory are being applied to the display. The signals identifying the row and column of activated keys are provided in a return signal line of the serial data bus.
摘要翻译： 独特的接口适配器通过三线自定时串行数据总线耦合到微处理器，用于容纳二十键键盘和八位显示器。 接口适配器包括用于从串行数据总线的两个正向信号线上发送的数据信号中恢复时钟信号和不归零（NRZ）数据信号的电路。 NRZ数据信号被移入接收寄存器，其中地址电路解码数据信号的地址部分以提供片选信号，并且控制电路对数据信号的控制部分进行解码以提供寄存器选择信号，读/写信号 和总线感测信号。 寄存器选择信号确定是否要对数据信号的数据部分的读/写信号响应加载控制寄存器或显示寄存器。 控制寄存器信号激活指示LED的四个状态，向显示器供电，在十位或十六位数显示之间进行选择，启用音频发生器并复位状态位触发器。 显示寄存器接收存储在显示存储器中的两个BCD数字。 键盘的键被扫描同时从显示存储器读出的数字被应用于显示器。 识别激活的键的行和列的信号被提供在串行数据总线的返回信号线中。
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