-
1.发明授权Process for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistors 失效用于制造包括具有自对准硅层和相关晶体管层的非易失性存储单元的集成结构的工艺
公开(公告)号：US4719184A
公开(公告)日：1988-01-12
申请号：US22482
申请日：1987-03-06
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/26
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11543 , H01L27/105 , Y10S438/942
摘要： After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.
摘要翻译： 在栅极氧化物生长之后，沉积和分离第一多晶硅层，电介质氧化物的生长和其从晶体管区域的去除，以及沉积第二多晶层，单个掩模使得可以首先蚀刻第二硅层和 电介质氧化物，然后在电池和晶体管区域的侧面处的栅极氧化物的第一硅层。
-
2.发明授权Method for erasing an electrically programmable and erasable non-volatile memory cell 失效擦除电可编程和可擦除非易失性存储单元的方法
公开(公告)号：US5784319A
公开(公告)日：1998-07-21
申请号：US788530
申请日：1997-01-24
CPC分类号： G11C16/14
摘要： A method for erasing an electrically programmable and erasable non-volatile memory cell having a control electrode, an electrically-insulated electrode and a first electrode. The method provides for coupling the control electrode to a first voltage supply and coupling the first electrode to a second voltage supply. The first voltage supply and the second voltage supply are suitable to cause tunneling of electric charges between the electrically-insulated electrode and the first electrode. The method also provides for a constant current to flow between the second voltage supply and the first electrode of the memory cell for at least part of an erasing time of the memory cell, the constant current having a prescribed value.
摘要翻译： 一种用于擦除具有控制电极，电绝缘电极和第一电极的电可编程和可擦除非易失性存储单元的方法。 该方法提供将控制电极耦合到第一电压源并将第一电极耦合到第二电压源。 第一电压源和第二电压源适于在电绝缘电极和第一电极之间引起电荷的隧穿。 该方法还提供恒定电流在存储器单元的第二电压源和第一电极之间流动，用于存储单元的擦除时间的至少一部分，恒定电流具有规定值。
-
3.发明授权Process for fabricating integrated devices including flash-EEPROM memories and transistors 失效用于制造包括闪存EEPROM存储器和晶体管的集成器件的工艺
公开(公告)号：US5637520A
公开(公告)日：1997-06-10
申请号：US195369
申请日：1994-02-10
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/11546 , H01L27/105 , Y10S438/981
摘要： A process for simultaneously fabricating a flash-EEPROM memory and circuit transistors using a DPCC process. A first polysilicon layer is not removed from the circuit area, and the gate regions of a circuit transistors are formed by shorting first and second polysilicon layers. A thin tunnel oxide layer of the memory cells is formed using the same mask provided for implanting boron into the cell area of the substrate. Following implantation and without removing the mask, the gate oxide formed previously over the whole surface of the wafer is removed from the cell area; the boron implant mask is removed; and tunnel oxidation is performed to increase the thickness of the tunnel oxide by a desired amount, and to slightly increase the thickness of the oxide in the transistor area.
摘要翻译： 使用DPCC工艺同时制造闪存EEPROM存储器和电路晶体管的过程。 不从电路区域去除第一多晶硅层，并且通过使第一和第二多晶硅层短路来形成电路晶体管的栅极区域。 存储单元的薄隧道氧化物层使用用于将硼注入到衬底的单元区域中的相同掩模形成。 在注入并且不去除掩模之后，先前在晶片的整个表面上形成的栅极氧化物从电池区域中去除; 去除硼注入掩模; 并且进行隧道氧化以将隧道氧化物的厚度增加所需量，并且稍微增加晶体管区域中的氧化物的厚度。
-
-
搜索结果
3 条记录 (耗时 0.015 秒)
