公开(公告)号：US6087729A

公开(公告)日：2000-07-11

申请号：US62378

申请日：1998-04-17

申请人： Gianfranco Cerofolini ,  Giorgio De Santi ,  Giuseppe Crisenza

发明人： Gianfranco Cerofolini ,  Giorgio De Santi ,  Giuseppe Crisenza

IPC分类号： C01B33/12 ,  C08F292/00 ,  C08L51/10 ,  H01B3/30 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

CPC分类号： H01B3/30 ,  C08F292/00 ,  H01L23/5329 ,  H01L2924/0002 ,  Y02P20/544

摘要： An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is formed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

摘要翻译： 层叠的导电层之间的绝缘膜通过其形成集成电路的互连，其中无机氧化物的气凝胶由有机单体在惰性离子轰击下接枝并依次进一步掺入气凝胶中以至少部分地填充 无机气凝胶的孔隙率。 复合介电材料是热稳定的并且具有令人满意的热预算。 形成气凝胶膜的方法包括将前体化合物溶液旋转到晶片上，然后在纺丝室中进行超临界溶剂萃取。

公开(公告)号：US5568418A

公开(公告)日：1996-10-22

申请号：US447772

申请日：1995-05-23

申请人： Giuseppe Crisenza ,  Cesare Clementi

发明人： Giuseppe Crisenza ,  Cesare Clementi

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  G11C11/34

CPC分类号： H01L27/11526 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L27/115

摘要： A method comprising the steps of depositing a first and second polysilicon layer, separated by an oxide layer; selectively etching the second polysilicon layer to form first gate regions; forming first substrate regions in the substrate and laterally in relation to the first gate regions; selectively etching the first polysilicon layer to form second gate regions of a length greater than the first gate regions; and forming in the substrate, laterally in relation to the second gate regions and partially overlapping the first substrate regions, second substrate regions of a higher doping level than the first substrate regions.

摘要翻译： 一种方法，包括沉积由氧化物层分离的第一和第二多晶硅层的步骤; 选择性地蚀刻第二多晶硅层以形成第一栅极区; 在所述衬底中形成第一衬底区域并相对于所述第一栅极区域侧向地形成; 选择性地蚀刻第一多晶硅层以形成长度大于第一栅极区域的第二栅极区域; 以及在所述衬底中相对于所述第二栅极区域横向地形成并且部分地与所述第一衬底区域重叠的第二衬底区域具有比所述第一衬底区域更高的掺杂水平。

公开(公告)号：US5464784A

公开(公告)日：1995-11-07

申请号：US129689

申请日：1993-09-30

申请人： Giuseppe Crisenza ,  Cesare Clementi

发明人： Giuseppe Crisenza ,  Cesare Clementi

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/266

CPC分类号： H01L27/11526 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/11546 ,  H01L27/105

摘要： A method comprising the steps of depositing a first and second polysilicon layer, separated by an oxide layer; selectively etching the second polysilicon layer to form first gate regions; forming first substrate regions in the substrate and laterally in relation to the first gate regions; selectively etching the first polysilicon layer to form second gate regions of a length greater than the first gate regions; and forming in the substrate, laterally in relation to the second gate regions and partially overlapping the first substrate regions, second substrate regions of a higher doping level than the first substrate regions.

摘要翻译： 一种方法，包括沉积由氧化物层分离的第一和第二多晶硅层的步骤; 选择性地蚀刻第二多晶硅层以形成第一栅极区; 在所述衬底中形成第一衬底区域并相对于所述第一栅极区域侧向地形成; 选择性地蚀刻第一多晶硅层以形成长度大于第一栅极区域的第二栅极区域; 以及在所述衬底中相对于所述第二栅极区域横向地形成并且部分地与所述第一衬底区域重叠的第二衬底区域具有比所述第一衬底区域更高的掺杂水平。

公开(公告)号：US5798279A

公开(公告)日：1998-08-25

申请号：US469431

申请日：1995-06-06

申请人： Giuseppe Crisenza ,  Cesare Clementi

发明人： Giuseppe Crisenza ,  Cesare Clementi

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L27/115

摘要： A method comprising the steps of depositing a first and second polysilicon layer, separated by an oxide layer; selectively etching the second polysilicon layer to form first gate regions; forming first substrate regions in the substrate and laterally in relation to the first gate regions; selectively etching the first polysilicon layer to form second gate regions of a length greater than the first gate regions; and forming in the substrate, laterally in relation to the second gate regions and partially overlapping the first substrate regions, second substrate regions of a higher doping level than the first substrate regions.

摘要翻译： 一种方法，包括沉积由氧化物层分离的第一和第二多晶硅层的步骤; 选择性地蚀刻第二多晶硅层以形成第一栅极区; 在所述衬底中形成第一衬底区域并相对于所述第一栅极区域侧向地形成; 选择性地蚀刻第一多晶硅层以形成长度大于第一栅极区域的第二栅极区域; 以及在所述衬底中相对于所述第二栅极区域横向地形成并且部分地与所述第一衬底区域重叠的第二衬底区域具有比所述第一衬底区域更高的掺杂水平。

公开(公告)号：US5717636A

公开(公告)日：1998-02-10

申请号：US642325

申请日：1996-05-03

申请人： Marco Dallabora ,  Giovanni Campardo ,  Giuseppe Crisenza

发明人： Marco Dallabora ,  Giovanni Campardo ,  Giuseppe Crisenza

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C16/00

CPC分类号： G11C16/0416 ,  H01L27/115

摘要： In a flash-EEPROM array, the cells in each row are grouped into pairs connected to the same diffused source line and to two different diffused bit lines, and the adjacent pairs of cells are spaced so that, in each row, only one cell is connected to a respective diffused bit line. The array presents global bit lines in the form of metal lines, and each connected to a plurality of diffused local bit lines, at least one for each sector. For each sector and each global bit line, there are provided two diffused local bit lines connected to the same respective global bit line by selection transistors so that only one local bit line is biased each time.

摘要翻译： 在闪存EEPROM阵列中，每行中的单元被分组成连接到相同的扩散源极线和两个不同的扩散位线的对，并且相邻的单元对间隔开，使得在每行中只有一个单元是 连接到相应的扩散位线。 该阵列呈现金属线形式的全局位线，并且每个连接到多个扩散的局部位线，每个扇区至少一个。 对于每个扇区和每个全局位线，提供通过选择晶体管连接到相同的各个全局位线的两个扩散的局部位线，使得每次只有一个局部位线被偏置。

公开(公告)号：US5508956A

公开(公告)日：1996-04-16

申请号：US214049

申请日：1994-03-15

申请人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

发明人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/0416 ,  G11C16/04 ,  G11C16/30

摘要： To reduce the number of depleted cells and the errors caused thereby, the memory array includes groups of control transistors corresponding to groups of memory cells. The control transistors of each group are NMOS transistors having the drain terminal connected to a control line. Each of the control transistors corresponds to a row portion of the memory array. Each control transistor has a control gate connected to a respective word line and a source region connected by a respective source line to the source regions of the memory cells in the same row and group.

摘要翻译： 为了减少耗尽的单元的数量和由此引起的误差，存储器阵列包括对应于存储器单元组的一组控制晶体管。 每组的控制晶体管是具有连接到控制线的漏极端子的NMOS晶体管。 每个控制晶体管对应于存储器阵列的行部分。 每个控制晶体管具有连接到相应字线的控制栅极和由相应源极线连接到相同行和组中的存储器单元的源极区域的源极区域。

公开(公告)号：US06187683B1

公开(公告)日：2001-02-13

申请号：US09059740

申请日：1998-04-14

申请人： Giorgio De Santi ,  Luca Zanotti ,  Giuseppe Crisenza

发明人： Giorgio De Santi ,  Luca Zanotti ,  Giuseppe Crisenza

IPC分类号： H01L21311

CPC分类号： H01L21/31053 ,  H01L21/31051 ,  H01L21/31055 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

摘要： A planarization method is disclosed to provide improved protection against cracking of the final passivation layer of integrated circuit devices. In one embodiment, such method includes final passivation of an integrated circuit device including at least one integrated circuit chip. Such final passivation includes the step of forming a layer of protective material over a top surface of the integrated circuit chip, and a subsequent step of planarizing such layer of protective material to obtain a protection layer having a substantially flat top surface.

摘要翻译： 公开了一种平面化方法，以提供改进的防止集成电路器件的最终钝化层破裂的保护。 在一个实施例中，这种方法包括包括至少一个集成电路芯片的集成电路器件的最终钝化。 这种最终钝化包括在集成电路芯片的顶表面上形成保护材料层的步骤，以及随后的平坦化这种保护材料层以获得具有基本平坦的顶表面的保护层的步骤。

公开(公告)号：US5977586A

公开(公告)日：1999-11-02

申请号：US455570

申请日：1995-05-31

申请人： Giuseppe Crisenza ,  Cesare Clementi

发明人： Giuseppe Crisenza ,  Cesare Clementi

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/11526 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/11546 ,  H01L27/105

摘要： A non-volatile integrated device having first and second dimensionally different polysilicon gate layers separated by an oxide layer for hot-carrier reliability. More specifically, the oxide and second polysilicon gate layer are selectively etched to form a second gate region over the first polysilicon gate layer that electrically contacts the first polysilicon gate in one direction and is isolated by the oxide in the other direction. Insulating sidewalls are formed over the first polysilicon gate layer regions that are not electrically contacted by the second gate layer to help isolate the second polysilicon gate and form an LDD structure within the substrate for the device.

摘要翻译： 一种非易失性集成器件，具有由氧化物层隔开的第一和第二尺寸不同的多晶硅栅极层，用于热载体的可靠性。 更具体地，选择性地蚀刻氧化物和第二多晶硅栅极层，以在第一多晶硅栅极层上形成在一个方向上与第一多晶硅栅极电接触并在另一个方向上被氧化物隔离的第二栅极区。 绝缘侧壁形成在不与第二栅极层电接触的第一多晶硅栅极层区域上，以帮助隔离第二多晶硅栅极并在器件的衬底内形成LDD结构。

公开(公告)号：US5633822A

公开(公告)日：1997-05-27

申请号：US458346

申请日：1995-06-02

申请人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

发明人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/02

CPC分类号： G11C16/04 ,  G11C16/0416 ,  G11C16/30

摘要： A method for writing cells in a memory which reduces errors caused by depleted memory array cells being turned on even when not selected. In the method, nonselected bit lines and nonselected word lines are biased so that the threshold voltage of the nonselected cells increases. In particular, the nonselected bit lines are left floating and the nonselected word lines are set to a zero voltage. Appropriate potentials are applied to the selected word line, selected bit line, and selected source line in order to program the selected cell.

摘要翻译： 一种用于将存储器中的单元写入的方法，其减少由耗尽的存储器阵列单元导致的错误，即使在未选择的情况下也被导通。 在该方法中，非选择位线和非选择字线被偏置，使得非选择单元的阈值电压增加。 特别地，非选定的位线保持浮动，并且非选择的字线被设置为零电压。 适当的电位被施加到所选择的字线，所选位线和所选择的源极线以便对所选择的单元进行编程。

公开(公告)号：US6067250A

公开(公告)日：2000-05-23

申请号：US311257

申请日：1999-05-13

申请人： Leonardo Ravazzi ,  Giuseppe Crisenza

发明人： Leonardo Ravazzi ,  Giuseppe Crisenza

IPC分类号： G11C29/02 ,  G11C29/50 ,  H01L27/115 ,  G11C16/06

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  H01L27/115 ,  G11C16/04 ,  G11C2029/5006

摘要： Method for localizing point defects causing column leakage currents in a non-volatile memory device, said device including a plurality of memory cells arranged in rows and columns in a matrix structure, the columns being connected to drain regions by first contacts, source diffusions, and metal lines which connect the source diffusions to each other by second contacts. The method includes the steps of modifying the memory device in order to eliminate a part of the first contacts and all the second contacts, and to form third contacts, which connect the metal lines to drain regions in rows wherein the first contacts have been eliminated, making the source diffusions independent of each other and halving the initial number of the memory cells; sequentially biasing the single columns of the matrix; sequentially biasing the single rows of the matrix, keeping biased one column; localizing a memory cell which presents the point defects, when the leakage current flow occurs.

摘要翻译： 用于定位导致非易失性存储器件中的列泄漏电流的点缺陷的方法，所述器件包括以矩阵结构排列成行和列的多个存储单元，所述列通过第一触点，源扩散和 通过第二接触将源极扩散连接的金属线。 该方法包括以下步骤：修改存储器件以消除第一触点和所有第二触点的一部分，以及形成第三触点，其将金属线连接到其中已经消除了第一触点的行中的漏极区域， 使源扩散彼此独立，并使存储器单元的初始数量减半; 顺序地偏置矩阵的单列; 顺序偏置矩阵的单行，保持偏置一列; 当发生漏电流时，对存在存在故障点的存储单元进行定位。