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公开(公告)号：US09996363B2
公开(公告)日：2018-06-12
申请号：US13435733
申请日：2012-03-30
申请人： Tom Cooksey , Jon Erik Oterhals , Jørn Nystad , Lars Ericsson , Eivind Liland , Daren Croxford
发明人： Tom Cooksey , Jon Erik Oterhals , Jørn Nystad , Lars Ericsson , Eivind Liland , Daren Croxford
CPC分类号： G06F9/451 , G06T1/60 , G09G5/14 , G09G5/393 , G09G5/397 , G09G2310/04 , G09G2320/103 , G09G2340/10 , G09G2360/122
摘要： In a compositing window system, as a respective version of the window for an application is written into a window buffer, a corresponding set of per tile signatures indicative of the content of each respective tile in the window buffer is generated and stored. When an updated version of the window is stored into a window buffer, the set of signature values for the updated version is compared to the set of signature values for the previous version in the window buffer to determine which tiles' content has changed. The set of tiles found to have changed is used to generate a set of regions for a window compositor to write to a window in a display frame buffer to update the window in the display frame buffer to display the new version of the window.
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公开(公告)号：US09158941B2
公开(公告)日：2015-10-13
申请号：US11376733
申请日：2006-03-16
CPC分类号： G06F21/79 , G06F12/145 , G06F21/74
摘要： A data processing apparatus and method are provided for managing access to content within the data processing apparatus. The data processing apparatus has a secure domain and a non-secure domain and comprises at least one device which is operable when seeking to access content stored in memory to issue a memory access request pertaining to either the secure domain or the non-secure domain. Further, writeable memory is provided which can store content required by the at least one device, with the writeable memory having at least one read only region whose content is stored therein under control of a secure task, the secure task being a task executed by one of the devices in the secure domain. Protection logic is then used in association with the writeable memory, which on receipt of a memory access request seeking to access content in the at least one read only region, prevents access to that read only region if that memory access request pertains to the non-secure domain and is seeking to write content to the read only region. This enables the speed, power and flexibility benefits of placing content in writeable memory to be achieved without prejudicing the security of that content, by ensuring that that content cannot be modified from the non-secure domain.
摘要翻译： 提供了一种用于管理对数据处理装置内的内容的访问的数据处理装置和方法。 数据处理装置具有安全域和非安全域，并且包括至少一个设备，当设法访问存储在存储器中的内容以发布与安全域或非安全域相关的存储器访问请求时可操作。 此外，提供可写存储器，其可以存储至少一个设备所需的内容，其中可写存储器具有至少一个只读区域，其内容在安全任务的控制下存储在其中，该安全任务是由一个执行的任务 的安全域中的设备。 然后，与可写存储器相关联地使用保护逻辑，其在接收到寻求访问所述至少一个只读区域中的内容的存储器访问请求时，如果该存储器访问请求涉及非可读存储器访问请求， 并且正在寻求将内容写入只读区域。 这使得通过确保不能从非安全域修改该内容，可以实现将内容放置在可写入内存中的速度，功率和灵活性，而不会影响该内容的安全性。
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公开(公告)号：US20110074800A1
公开(公告)日：2011-03-31
申请号：US12588461
申请日：2009-10-15
申请人： Ashley Stevens , Elvind Liland , Daren Croxford , Joe Tapply
发明人： Ashley Stevens , Elvind Liland , Daren Croxford , Joe Tapply
IPC分类号： G09G5/36
CPC分类号： G06T11/40
摘要： A graphics processing system includes a graphics processor 1 that renders output frames that are written to a frame buffer in a memory 2 for display on a display 7. Comparison and control hardware 5 of the graphics processing system operates to compare successive output frames that are being generated for display, and then controls one or more aspects of the way in which the display of the output frames generated by the graphics processor 1 is carried out. In one preferred embodiment, the rate at which the display device 7 is updated (refreshed) from the frame buffer is controlled on the basis of the output frame comparisons. In another preferred embodiment, the format used when storing the output frames in the frame buffer is selected on the basis of the output frame comparisons.
摘要翻译： 图形处理系统包括图形处理器1，其将写入存储器2中的帧缓冲器的输出帧呈现以在显示器7上显示。图形处理系统的比较和控制硬件5用于比较正在 生成用于显示，然后控制执行由图形处理器1生成的输出帧的显示的方式的一个或多个方面。 在一个优选实施例中，基于输出帧比较来控制显示设备7从帧缓冲器更新（刷新）的速率。 在另一优选实施例中，基于输出帧比较选择在帧缓冲器中存储输出帧时使用的格式。
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公开(公告)号：US07640397B2
公开(公告)日：2009-12-29
申请号：US11545758
申请日：2006-10-11
IPC分类号： G06F13/00
CPC分类号： G06F12/0864 , G06F12/0895 , G06F2212/1028 , Y02D10/13
摘要： A memory has multiple memory rows 32 storing respective stored values. The stored values are divided into portions which may be shared by all stored values within the memory rows concerned. When such portions are so shared, then the comparison between an input value and the plurality of stored values can be performed using a base value stored within a base value register 30 rather than by reading the relevant portions of the memory rows. Thus, those relevant portions of the memory rows can be disabled and power saved.
摘要翻译： 存储器具有存储相应存储值的多个存储器行32。 存储的值被划分成可以被相关存储器行内的所有存储值共享的部分。 当这样的部分如此共享时，可以使用存储在基值寄存器30内的基值进行输入值与多个存储值之间的比较，而不是通过读取存储器行的相关部分。 因此，可以禁用存储器行的相关部分并省电。
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公开(公告)号：US07558938B2
公开(公告)日：2009-07-07
申请号：US11349348
申请日：2006-02-08
申请人： Daren Croxford
发明人： Daren Croxford
IPC分类号： G06F12/00
摘要： Encoding of logical addresses LA upon an off-chip memory bus 22 is performed to produce encoded addresses EA. The portion of the logical address encoded LA [9:3] does not include the least significant bits LA [2:0]. The number of bits LA [2:0] which are unencoded is chosen to correspond to a burst length BL supported by the memory 6 being accessed. Thus, burst mode accesses can be serviced by the memory 6 incrementing its memory address in the normal way. The encoding performed, such as Gray Encoding, reduces the Hamming distance between adjacent memory addresses in a sequence of memory addresses so as to reduce energy consumption.
摘要翻译： 执行在片外存储器总线22上的逻辑地址LA的编码以产生编码地址EA。 编码LA [9：3]的逻辑地址的部分不包括最低有效位LA [2：0]。 未编码的位数LA [2：0]被选择为对应于被访问的存储器6支持的突发长度BL。 因此，突发模式访问可以由存储器6以正常方式递增其存储器地址来服务。 执行的编码，例如灰度编码，减少了存储器地址序列中的相邻存储器地址之间的汉明距离，以便降低能量消耗。
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公开(公告)号：US20090100054A1
公开(公告)日：2009-04-16
申请号：US12230333
申请日：2008-08-27
CPC分类号： G06F12/0864 , G06F12/0895 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： Data store access circuitry is disclosed that comprises: a data store for storing values; comparator circuitry coupled to said data store and responsive to receipt of a data access request comprising an address to compare at least a portion of said address with at least a portion of one or more of said values stored in said data store so as to identify a stored value matching said address; a base value register coupled to said comparator circuitry and storing a base value corresponding to at least a portion of at least one of said stored values; and comparator control circuitry coupled to said comparator circuitry to control: (i) which portion of said address is processed as a non-shared portion and compared by said comparator circuitry with non-shared portions of said one or more stored values stored in said data store; and (ii) which portion of said address is processed as a shared portion and compared by said comparator circuitry with a shared portion of said base value stored in said base value register; wherein said shared portion of said base value has a value matching corresponding portions of all of said stored values stored within said data store.
摘要翻译： 公开了一种数据存储器访问电路，其包括：用于存储值的数据存储器; 比较器电路，耦合到所述数据存储器并且响应于接收包括地址的数据访问请求，以将所述地址的至少一部分与存储在所述数据存储器中的一个或多个所述值的至少一部分进行比较，以便识别 存储值匹配所述地址; 基值寄存器，耦合到所述比较器电路并存储对应于所述存储值中的至少一个的至少一部分的基值; 和比较器控制电路，其耦合到所述比较器电路以控制：（i）所述地址的哪个部分被处理为非共享部分，并由所述比较器电路与所存储在所述数据中的所述一个或多个存储值的非共享部分进行比较 商店; 和（ii）所述地址的哪个部分被处理为共享部分，并由所述比较器电路与存储在所述基值寄存器中的所述基值的共享部分进行比较; 其中所述基本值的所述共享部分具有匹配存储在所述数据存储器内的所有所述存储值的相应部分的值。
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公开(公告)号：US20070226387A1
公开(公告)日：2007-09-27
申请号：US11363270
申请日：2006-02-28
申请人： Daren Croxford
发明人： Daren Croxford
IPC分类号： G06F13/38
CPC分类号： G06F13/4013 , G06F13/4018 , Y02D10/14 , Y02D10/151 , Y10S707/99935 , Y10S707/99936
摘要： In a system having a first device 10 and a second device 8 between which data values are transferred via an N-bit bus, a resizing unit 18 and an M-bit bus, reordering of the data is performed such that portions of the original N-bit data words having a high degree of bit-value correlation are grouped together as successive transfers thereby reducing the Hamming distance between successive transfers in a manner that reduces energy consumption.
摘要翻译： 在具有第一设备10和第二设备8的系统中，数据值经由N位总线，调整大小单元18和M位总线传送，执行数据的重新排序，使得原始N 具有高度比特值相关性的位数据字被分组在一起作为连续传输，从而以降低能量消耗的方式减少连续传送之间的汉明距离。
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公开(公告)号：US09406155B2
公开(公告)日：2016-08-02
申请号：US12923518
申请日：2010-09-24
申请人： Jon Erik Oterhals , Daren Croxford , Lars Ericsson , Jørn Nystad , Eivind Liland
发明人： Jon Erik Oterhals , Daren Croxford , Lars Ericsson , Jørn Nystad , Eivind Liland
CPC分类号： G06T11/40 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2310/04 , G09G2320/103
摘要： A graphics processor 1 includes after its tile rendering logic 40, a transaction elimination unit 5 that includes data block generation logic 41 and block comparison logic 43. The block generation logic 41 generates data blocks from the rendered tiles produced by the tile rendering logic 40. The data blocks are then stored in buffers 42. Comparison logic 43 then compares a new data block with the previous data block (which will already be stored in the buffers 42), and generates an output metadata bit indicating whether the blocks can be considered to be the same or not, on the basis of the comparison. The meta-data output bits are stored appropriately in a meta-data bitmap 45 in main memory 2 that is associated with the output data array in question. If the blocks are determined to be different by the comparison logic then the new data block is written from the buffers 42 to the frame buffer 44 in the main memory 2. On the other hand, if the two blocks are considered to be similar to each other, the new block is not written into the data array in the frame buffer 44.
摘要翻译： 图形处理器1包括在其瓦片渲染逻辑40之后的包括数据块生成逻辑41和块比较逻辑43的事务消除单元5.块生成逻辑41从由瓦片渲染逻辑40产生的渲染瓦片生成数据块。 然后将数据块存储在缓冲器42中。然后，比较逻辑43将新的数据块与先前的数据块（其将已经存储在缓冲器42中）进行比较，并且产生一个输出元数据位，指示是否可以将块视为 在不同的基础上进行比较。 元数据输出位被适当地存储在与所讨论的输出数据阵列相关联的主存储器2中的元数据位图45中。 如果通过比较逻辑确定块是不同的，则将新数据块从缓冲器42写入主存储器2中的帧缓冲器44.另一方面，如果两个块被认为与每个块相似 另一方面，新的块不被写入帧缓冲器44中的数据阵列。
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公开(公告)号：US08255673B2
公开(公告)日：2012-08-28
申请号：US12149088
申请日：2008-04-25
申请人： Daniel Kershaw , Daren Croxford
发明人： Daniel Kershaw , Daren Croxford
IPC分类号： G06F12/00
CPC分类号： G06F12/1491 , G06F21/52
摘要： Apparatus for processing data is provided comprising processing circuitry and monitoring circuitry for monitoring write transactions and performing transaction authorizations of certain transactions in dependence upon associated memory addresses. The processing circuitry is configured to enable execution of a write instruction corresponding to a write transaction to be monitored to continue to completion while the monitoring circuitry is performing monitoring of the write transactions and the monitoring circuitry is arranged to cause storage of write transaction data in an intermediate storage element for those transactions for which an authorization is required. Storage of write transaction data in an intermediate storage element enables the write transaction to be reissued in dependence upon the result of the transaction authorization although the corresponding write instruction has already completed.
摘要翻译： 提供了用于处理数据的装置，其包括处理电路和监控电路，用于根据相关的存储器地址来监视写事务和执行某些事务的交易授权。 处理电路被配置为使得能够执行与待监视的写事务相对应的写指令以继续完成，同时监视电路正在执行对写事务的监视，并且监视电路被布置成使写事务数据存储在 需要授权的那些交易的中间存储元件。 将写入事务数据存储在中间存储元件中使得能够根据交易授权的结果重新发行写入事务，尽管相应的写入指令已经完成。
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公开(公告)号：US07991960B2
公开(公告)日：2011-08-02
申请号：US12230333
申请日：2008-08-27
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/0895 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： Data store access circuitry is disclosed that comprises: a data store for storing values; comparator circuitry coupled to said data store and responsive to receipt of a data access request comprising an address to compare at least a portion of said address with at least a portion of one or more of said values stored in said data store so as to identify a stored value matching said address; a base value register coupled to said comparator circuitry and storing a base value corresponding to at least a portion of at least one of said stored values; and comparator control circuitry coupled to said comparator circuitry to control: (i) which portion of said address is processed as a non-shared portion and compared by said comparator circuitry with non-shared portions of said one or more stored values stored in said data store; and (ii) which portion of said address is processed as a shared portion and compared by said comparator circuitry with a shared portion of said base value stored in said base value register; wherein said shared portion of said base value has a value matching corresponding portions of all of said stored values stored within said data store.
摘要翻译： 公开了一种数据存储器访问电路，其包括：用于存储值的数据存储器; 比较器电路，耦合到所述数据存储器并且响应于接收包括地址的数据访问请求，以将所述地址的至少一部分与存储在所述数据存储器中的一个或多个所述值的至少一部分进行比较，以便识别 存储值匹配所述地址; 基值寄存器，耦合到所述比较器电路并存储对应于所述存储值中的至少一个的至少一部分的基值; 和比较器控制电路，其耦合到所述比较器电路以控制：（i）所述地址的哪个部分被处理为非共享部分，并由所述比较器电路与所存储在所述数据中的所述一个或多个存储值的非共享部分进行比较 商店; 和（ii）所述地址的哪个部分被处理为共享部分，并由所述比较器电路与存储在所述基值寄存器中的所述基值的共享部分进行比较; 其中所述基本值的所述共享部分具有匹配存储在所述数据存储器内的所有所述存储值的相应部分的值。
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