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公开(公告)号：US07752627B2
公开(公告)日：2010-07-06
申请号：US11051980
申请日：2005-02-04
CPC分类号： G06F9/3851 , G06F9/3814 , G06F9/3861 , G06F9/4881 , Y02D10/24
摘要： A leaky-bucket style thread scheduler for scheduling concurrent execution of multiple threads in a microprocessor is provided. The execution pipeline notifies the scheduler when it has completed instructions. The scheduler maintains a virtual water level for each thread and decreases it each time the execution pipeline executes an instruction of the thread. The scheduler includes an instruction execution rate for each thread. The scheduler increases the virtual water level based on the requested rate per a predetermined number of clock cycles. The scheduler includes virtual water pressure parameters that define a set of virtual water pressure ranges over the height of the virtual water bucket. When a thread's virtual water level moves from one virtual water pressure range to the next higher range, the scheduler increases the instruction issue priority for the thread; conversely, when the level moves down, the scheduler decreases the instruction issue priority for the thread.
摘要翻译： 提供了一种漏斗式线程调度器，用于调度微处理器中多个线程的并发执行。 执行流水线在完成指令后通知调度程序。 调度程序为每个线程维护一个虚拟水位，并在每次执行流水线执行线程指令时减小它。 调度器包括每个线程的指令执行率。 调度器基于每预定数量的时钟周期的请求速率增加虚拟水位。 调度器包括限定虚拟水桶高度上的一组虚拟水压力范围的虚拟水压参数。 当线程的虚拟水位从一个虚拟水压范围移动到下一个较高范围时，调度程序增加线程的指令发出优先级; 相反，当电平下降时，调度器减少线程的指令发出优先级。
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2.发明授权Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency 有权具有优化线程调度器的多线程微处理器，可提高管道利用效率公开(公告)号：US08151268B2
公开(公告)日：2012-04-03
申请号：US12684564
申请日：2010-01-08
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/30087 , G06F9/3009 , G06F9/3867
摘要： A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline. One or more instructions in the pipeline of the thread context associated with the thread context flush signal can be flushed or nullified.
摘要翻译： 提供了用于同时执行多个线程的多线程处理器。 该处理器包括一个执行流水线和一个线程调度器，它将线程的指令分派到执行流水线。 执行流水线被配置为当线程上下文的一个或多个指令在执行流水线中停止时，生成与线程上下文相关联的线程上下文（TC）刷新指示符。 与线程上下文冲洗信号相关联的线程上下文中的一个或多个指令可被刷新或无效。
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3.发明授权Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions 有权多线程微处理器中的指令/滑动缓冲区，用于存储调度的指令，以避免重新获取刷新的指令公开(公告)号：US07853777B2
公开(公告)日：2010-12-14
申请号：US11051978
申请日：2005-02-04
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3802
摘要： An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads is disclosed. The apparatus includes a buffer for each thread that stores fetched instructions of the thread, having an indicator for indicating which of the fetched instructions in the buffer have already been dispatched for execution. An input for each thread indicates that one or more of the already-dispatched instructions in the buffer has been flushed from execution. Control logic for each thread updates the indicator to indicate the flushed instructions are no longer already-dispatched, in response to the input. This enables the processor to re-dispatch the flushed instructions from the buffer to avoid re-fetching the flushed instructions. In one embodiment, there are fewer buffers than threads, and they are dynamically allocatable by the threads. In one embodiment, a single integrated buffer is shared by all the threads.
摘要翻译： 公开了一种用于减少配置为并发执行多个线程的多线程处理器中的指令重新获取的装置。 该装置包括用于存储线程的获取的指令的每个线程的缓冲器，具有指示器，用于指示缓冲器中的哪个获取的指令已经被分派以执行。 每个线程的输入表示缓冲区中已经调度的指令中的一个或多个已经从执行刷新。 每个线程的控制逻辑更新指示器，以指示刷新的指令不再已经被调度，以响应输入。 这使得处理器能够从缓冲区重新分配刷新的指令，以避免重新获取刷新的指令。 在一个实施例中，存在比线程少的缓冲器，并且它们可被线程动态地分配。 在一个实施例中，单个集成缓冲器被所有线程共享。
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4.发明授权Smart memory based synchronization controller for a multi-threaded multiprocessor SoC 有权用于多线程多处理器SoC的基于智能内存的同步控制器公开(公告)号：US07594089B2
公开(公告)日：2009-09-22
申请号：US10955231
申请日：2004-09-30
CPC分类号： G06F12/1416 , G06F13/1642
摘要： A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of the memory system wherein the gating memory returns a particular one access method for a particular one memory location responsive to a memory access instruction relating to the particular one memory location, the interface including: a request storage for storing a plurality of concurrent memory access instructions for one or more of the particular memory locations, each the memory access instruction issued from an associated independent thread context; an arbiter, coupled to the request storage, for selecting a particular one of the memory access instructions to apply to the gating memory; and a controller, coupled to the request storage and to the arbiter, for: storing the plurality of memory access instructions in the request storage; initiating application of the particular one memory access instruction selected by the arbiter to the gating memory; receiving the particular one access method associated with the particular one memory access method from the gating memory; and initiating a communication of the particular access method to the thread context associated with the particular one access instruction.
摘要翻译： 一种与具有门控存储器的多处理存储器系统一起使用的存储器接口，门控存储器将一个或多个存储器访问方法与存储器系统的多个存储器位置中的每一个相关联，其中门控存储器返回特定的一个存取方法 一个存储器位置响应于与特定一个存储器位置相关的存储器访问指令，该接口包括：存储用于特定存储器位置中的一个或多个的多个并发存储器访问指令的请求存储器，每个存储器访问指令从 相关联的独立线程上下文; 耦合到所述请求存储器的仲裁器，用于选择所述存储器访问指令中的特定一个以应用于所述门控存储器; 以及耦合到请求存储器和仲裁器的控制器，用于：将多个存储器访问指令存储在请求存储器中; 启动由仲裁器选择的特定一个存储器访问指令到门控存储器的应用; 从门控存储器接收与特定一个存储器访问方法相关联的特定一个访问方法; 以及发起特定访问方法与特定一个访问指令相关联的线程上下文的通信。
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5.发明授权Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages 有权优先级线程选择部分基于在流水线阶段提供指令操作数寄存器使用的状态信息的失速可能性公开(公告)号：US07664936B2
公开(公告)日：2010-02-16
申请号：US11051998
申请日：2005-02-04
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/382 , G06F9/3838 , G06F9/3861
摘要： An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority generator that generates a priority for each instruction based on the register usage information and state information of instructions currently executing in an execution pipeline, and selection logic that dispatches at least one instruction from at least one thread based on the priority of the instructions. The priority indicates the likelihood the instruction will execute in the execution pipeline without stalling. For example, an instruction may have a high priority if it has little or no register dependencies or its data is known to be available; or may have a low priority if it has strong register dependencies or is an uncacheable or synchronized storage space load instruction.
摘要翻译： 提供了一种用于在多线程处理器中同时执行的多个线程之间调度指令调度的装置。 该装置包括：指令解码器，用于生成来自每个线程的指令的寄存器使用信息;基于寄存器使用信息和当前在执行流水线中执行的指令的状态信息生成每个指令的优先级的优先级生成器，以及选择 基于指令的优先级从至少一个线程调度至少一条指令的逻辑。 优先级表示指令在执行流水线中执行的可能性，而不会停顿。 例如，如果指令很少或没有寄存器依赖性或其数据已知可用，则指令可能具有高优先级; 或者如果具有强的寄存器依赖性或者不可缓存或同步的存储空间加载指令，则可能具有低优先级。
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6.发明授权Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency 有权具有优化线程调度器的多线程微处理器，可提高管道利用效率公开(公告)号：US07657891B2
公开(公告)日：2010-02-02
申请号：US11051979
申请日：2005-02-04
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/30087 , G06F9/3009 , G06F9/3867
摘要： A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline detects a stalling event caused by a dispatched instruction, and flushes the execution pipeline to enable instructions of other threads to continue executing. The execution pipeline communicates to the scheduler which thread caused the stalling event, and the scheduler stops dispatching instructions for the thread until the stalling condition terminates. In one embodiment, the execution pipeline only flushes the thread including the instruction that caused the event. In one embodiment, the execution pipeline stalls rather than flushing if the thread is the only runnable thread. In one embodiment, the processor includes skid buffers to which the flushed instructions are rolled back so the instruction fetch pipeline need not be flushed, only the execution pipeline.
摘要翻译： 提供了用于同时执行多个线程的多线程处理器。 该处理器包括一个执行流水线和一个线程调度器，它将线程的指令分派到执行流水线。 执行流水线检测由分派指令引起的停顿事件，并刷新执行流水线以使其他线程的指令能够继续执行。 执行流水线与调度程序进行通信，该线程引起停止事件，并且调度器停止线程的调度指令，直到停止条件终止。 在一个实施例中，执行流水线仅刷新包括引起事件的指令的线程。 在一个实施例中，如果线程是唯一的可运行线程，则执行流水线停止而不是刷新。 在一个实施例中，处理器包括滑动缓冲器，刷新的指令被回滚到所述缓冲器缓冲器，使得指令提取流水线不需要被刷新，仅仅是执行流水线。
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7.发明授权Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler 有权将外部线程优先处理策略实施逻辑与客户可修改寄存器连接到处理器内部调度程序公开(公告)号：US07613904B2
公开(公告)日：2009-11-03
申请号：US11051997
申请日：2005-02-04
IPC分类号： G06F9/50
CPC分类号： G06F9/3851
摘要： A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second portion to the core. The second portion implements a thread scheduling policy that may be customized to the customer's particular application. The first portion may be scheduling policy-agnostic and issues instructions of the threads each clock cycle to execution units based on the scheduling policy communicated by the second portion. The second portion communicates the scheduling policy via a priority for each of the threads. When the core commits an instruction for execution, the core communicates to the second portion which thread the committed instruction is in to enable the second portion to update the priorities in response thereto.
摘要翻译： 提供了一种用于调度在多线程处理器中并发执行的多个线程的指令的分支指令调度器。 调度器包括不可由客户定制的可重用核心内的第一部分，可定制的核心外部的第二部分以及将第二部分耦合到核心的接口。 第二部分实现可以根据客户的特定应用来定制的线程调度策略。 第一部分可以是调度策略无关的，并且基于由第二部分传送的调度策略，将线程的每个时钟周期的指令周期发送到执行单元。 第二部分通过每个线程的优先级来传送调度策略。 当核心提交执行指令时，核心与提交的指令所线程的第二部分进行通信，以使得第二部分响应于此而更新优先级。
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公开(公告)号：US07315937B2
公开(公告)日：2008-01-01
申请号：US10956490
申请日：2004-10-01
IPC分类号： G06F7/76
CPC分类号： G06F9/30018 , G06F9/30032
摘要： A method of extracting bits of a bit stream including retrieving bits from the bit stream into an accumulator, specifying a size value specifying a number of bits to extract, storing a position value into a control register, and executing a bit extraction instruction. The bit extraction instruction includes copying the size value number of bits from the accumulator beginning at the position value into a target register, setting any remaining bits of the target register to zero, and decrementing the position value by an amount based on the size value. The method may include loading bits from a bit stream into a register and moving the contents of the register into the accumulator to replenish the accumulator. The method may include determining, based on the position value, whether the accumulator needs to be replenished, and if not, branching to bypass replenishing functions.
摘要翻译： 提取比特流的比特的方法，包括从比特流中检索比特到累加器中，指定指定要提取的比特数的大小值，将位置值存储到控制寄存器中，以及执行比特提取指令。 比特提取指令包括将来自累加器的位置值开始的大小值比特数复制到目标寄存器中，将目标寄存器的任何剩余比特设置为零，并且基于大小值递减位置值。 该方法可以包括将比特流加载到寄存器中并将寄存器的内容移动到累加器中以补充累加器。 该方法可以包括基于位置值确定累加器是否需要被补充，如果不是，则分支到旁路补充功能。
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公开(公告)号：US08392663B2
公开(公告)日：2013-03-05
申请号：US12332291
申请日：2008-12-10
申请人： Ryan C. Kinter , Darren M. Jones , Matthias Knoth
发明人： Ryan C. Kinter , Darren M. Jones , Matthias Knoth
CPC分类号： G06F9/3834 , G06F9/30047 , G06F9/3812 , G06F9/3877 , G06F9/3885 , G06F12/0815
摘要： A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance operation. The first processor can determine whether the cache maintenance operation is a coherent operation. For coherent operations, the first processor sends a coherent request message for distribution to other processors in the coherent domain and can cancel execution of the cache maintenance operation pending receipt of intervention messages corresponding to the coherent request. The intervention messages can reflect a global ordering of coherence traffic in the multiprocessor system and can include instructions for maintaining a data cache and an instruction cache of the first processor. Cache maintenance operations that are determined to be non-coherent can be executed at the first processor without sending the coherent request.
摘要翻译： 多处理器系统保持连贯域中的处理器之间的高速缓存一致性。 在相干域内，第一处理器可以接收执行高速缓存维护操作的命令。 第一处理器可以确定高速缓存维护操作是否是一致的操作。 对于相干操作，第一处理器发送一致的请求消息以分发给相干域中的其他处理器，并且可以在收到对应于相干请求的干预消息之前取消高速缓存维护操作的执行。 干预消息可以反映多处理器系统中的一致性业务的全局排序，并且可以包括用于维护第一处理器的数据高速缓存和指令高速缓存的指令。 确定为非相干的高速缓存维护操作可以在第一处理器处执行，而不发送相干请求。
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10.发明授权Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion 有权使用地址索引值的微处理器指令能够以循环方式访问虚拟缓冲区公开(公告)号：US07873810B2
公开(公告)日：2011-01-18
申请号：US10956498
申请日：2004-10-01
CPC分类号： G06F9/3001 , G06F9/30181 , G06F9/3552
摘要： A modular subtraction instruction for execution on a microprocessor having at least one register. The instruction includes opcode bits for designating the instruction and operand bits for designating at least one register storing an offset index, a decrement value, and an address index. When the modular subtraction instruction is executed on the microprocessor, the address index is modified by the decrement value if the address index is not zero and is modified by the offset index if the address index is zero. For example, the address index is repeatedly decremented using the decrement value until it reaches zero, and then the address index is reset back to the offset index. The operand bits may include multiple fields identifying multiple registers selected from the general purpose registers of the microprocessor. The modular subtraction instruction enables access to a buffer in memory in circular fashion by virtue of its operation.
摘要翻译： 一种用于在具有至少一个寄存器的微处理器上执行的模块化减法指令。 该指令包括用于指定指令的操作码位和用于指定存储偏移索引，递减值和地址索引的至少一个寄存器的操作数位。 当在微处理器上执行模块化减法指令时，如果地址索引不为零，则地址索引将通过递减值进行修改，如果地址索引为零，则由偏移索引进行修改。 例如，地址索引使用递减值重复递减，直到它达到零，然后将地址索引重置回到偏移索引。 操作数位可以包括标识从微处理器的通用寄存器中选择的多个寄存器的多个字段。 模块化减法指令通过其操作使得能够以循环方式访问存储器中的缓冲器。
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