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公开(公告)号：US08381155B1
公开(公告)日：2013-02-19
申请号：US13200831
申请日：2011-10-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method of generating valid vertical interconnect positions for a multiple layer integrated circuit including multiple layers stacked vertically above one another and having a bonding interface between at least one pair of layers. The interface is formed by the coupling of a pair of conductive bond patterns formed on facing surfaces of the pair of layers. The method includes defining a candidate transformation origin, defining a sub-region which tessellates across the patterns, applying a predetermined transformation to the patterns at the bonding interface, determining the validity of the candidate transformation origin in dependence on coincidence of at least a subset of the patterns with the transformed patterns, selecting a valid transformation origin, and defining a set of valid vertical interconnect positions associated with the valid transformation origin at positions in the bonding interface where the original and transformed patterns coincided with each other.
摘要翻译： 一种生成用于多层集成电路的有效垂直互连位置的方法，所述多层集成电路包括彼此垂直堆叠并且具有至少一对层之间的结合界面的多个层。 界面由形成在一对层的相对表面上的一对导电键合图案的耦合形成。 所述方法包括定义候选变换原点，定义横跨所述模式进行细分的子区域，在所述接合界面处对所述模式应用预定变换，根据所述候选变换原点的至少一个子集的一致性来确定所述候选变换原点的有效性 具有变换的图案的图案，选择有效的变换原点，以及在原始和变换的图案彼此一致的接合界面中的位置处定义与有效变换原点相关联的一组有效的垂直互连位置。
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公开(公告)号：US07055007B2
公开(公告)日：2006-05-30
申请号：US10410602
申请日：2003-04-10
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.
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公开(公告)号：US07533226B2
公开(公告)日：2009-05-12
申请号：US11353024
申请日：2006-02-14
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.
摘要翻译： 描述了一种在数据处理电路中使用的存储器电路，其中存储单元具有至少两个状态，每个状态由对应于第一电源线的第一电压电平和对应于第二电源线的第二电压电平确定 。 存储电路包括可读状态，其中存储在存储单元中的信息是可读的，并且存储在所述存储单元中的信息被可靠地保留但不可读的不可读状态。 改变第一电压电平但保持第二电压电平基本上恒定会影响可读状态和不可读状态之间的转换。 在使用中，处于不可读状态的存储单元的静态功耗小于可读状态下的存储单元的静态功耗。
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公开(公告)号：US4510616A
公开(公告)日：1985-04-09
申请号：US577003
申请日：1984-02-06
CPC分类号： G06F17/5081 , G06K9/56
摘要： A pipeline of programmable serial neighborhood stages is used to automatically check for adherence to a set of predetermined geometrical constraints or design rules used in the fabrication of electronic components such as integrated circuit devices. In a disclosed embodiment, bit-map representations of several IC masks are superimposed in one composite image matrix for processing in the pipeline. Advantages in processing speed, especially for design rule checking requiring data from more than one mask, are obtained since all necessary data is available to the stages in the pipeline.
摘要翻译： 使用可编程序列相邻级的管线来自动检查对于诸如集成电路器件的电子部件的制造中使用的一组预定几何约束或设计规则的附着。 在公开的实施例中，几个IC掩模的位图表示叠加在一个合成图像矩阵中，用于在流水线中进行处理。 获得处理速度的优点，特别是对于需要来自多个掩模的数据的设计规则检查，因为所有必要的数据都可用于流水线的各个阶段。
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公开(公告)号：US4441207A
公开(公告)日：1984-04-03
申请号：US340609
申请日：1982-01-19
CPC分类号： G06K9/56 , G06F17/5081
摘要： A pipeline of programmable serial neighborhood stages is used to automatically check for adherence to a set of predetermined geometrical constraints or design rules used in the fabrication of electronic components such as integrated circuit devices. In a disclosed embodiment, bit-map representations of several IC masks are superimposed in one composite image matrix for processing in the pipeline. Advantages in processing speed, especially for design rule checking requiring data from more than one mask, are obtained since all necessary data is available to the stages in the pipeline.
摘要翻译： 使用可编程序列相邻级的管线来自动检查对于诸如集成电路器件的电子部件的制造中使用的一组预定几何约束或设计规则的附着。 在公开的实施例中，几个IC掩模的位图表示叠加在一个合成图像矩阵中，用于在流水线中进行处理。 获得处理速度的优点，特别是对于需要来自多个掩模的数据的设计规则检查，因为所有必要的数据都可用于流水线的各个阶段。
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公开(公告)号：US20120254491A1
公开(公告)日：2012-10-04
申请号：US13438920
申请日：2012-04-04
IPC分类号： G06F13/362
CPC分类号： G11C7/10 , G06F13/4022 , G06F2213/0038 , G11C7/1012 , H03K17/693
摘要： Interconnect circuitry 2 has a plurality of data source circuits 8 connected to respective input paths 4 and a plurality of data destination circuits 10 connected to respective output paths 6. Connection cells 12 provide selective connections between input paths 4 and output paths 6. Arbitration circuitry 26 provides adaptive priority arbitration between overlapping requests received at different input paths. Priority bits 16 within a matrix of priority bit 46 for each output path 10 are used to represent the priority relationships between different input paths which compete for access to that output path 10. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.
摘要翻译： 互连电路2具有连接到相应输入路径4的多个数据源电路8和连接到相应输出路径6的多个数据目的地电路10.连接单元12提供输入路径4和输出路径6之间的选择性连接。仲裁电路26 在不同输入路径上接收的重叠请求之间提供自适应优先级仲裁 用于每个输出路径10的优先级位46的矩阵内的优先级位16用于表示竞争对该输出路径10的访问的不同输入路径之间的优先级关系。更新操作按照每行或每列进行应用 矩阵来实现更新计划，例如最近最近授予的，最近授予的，轮回，逆转，掉期，最少选择权，最近授予的选择权。
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公开(公告)号：US07260694B2
公开(公告)日：2007-08-21
申请号：US11526687
申请日：2006-09-26
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.
摘要翻译： 描述了一种在数据处理电路中使用的存储器电路，其中存储单元具有至少两个状态，每个状态由对应于第一电源线的第一电压电平和对应于第二电源线的第二电压电平确定 。 存储电路包括可读状态，其中存储在存储单元中的信息是可读的，并且存储在所述存储单元中的信息被可靠地保留但不可读的不可读状态。 改变第一电压电平但保持第二电压电平基本上恒定会影响可读状态和不可读状态之间的转换。 在使用中，处于不可读状态的存储单元的静态功耗小于可读状态下的存储单元的静态功耗。
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