公开(公告)号：US08880866B2

公开(公告)日：2014-11-04

申请号：US13274138

申请日：2011-10-14

Applicant: Michael B. Doerr ,  Carl S. Dobbs ,  Michael B. Solka ,  Michael R. Trocino ,  David A. Gibson

Inventor： Michael B. Doerr ,  Carl S. Dobbs ,  Michael B. Solka ,  Michael R. Trocino ,  David A. Gibson

IPC: G06F1/24 ,  G06F9/00 ,  G06F21/71 ,  G06F15/76 ,  G06F15/173 ,  G06F15/163 ,  G06F15/167

CPC classification number: G06F21/71 ,  G06F3/0635 ,  G06F9/4405 ,  G06F13/00 ,  G06F13/4221 ,  G06F15/163 ,  G06F15/167 ,  G06F15/17343 ,  G06F15/177 ,  G06F15/76 ,  G06F21/575 ,  G06F2221/034

Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.

Abstract translation: 禁用多处理器结构中的通信。 多处理器结构可以包括多个处理器和多个通信元件，并且多个通信元件中的每一个可以包括存储器。 可以为多处理器结构接收配置，其指定禁用以下中的一个或多个：一个或多个处理器和一个或多个通信元件之间的通信路径; 一个或多个处理器和一个或多个其他处理器; 或一个或多个通信元件和一个或多个其他通信元件。 因此，多处理器结构可以被自动地配置在硬件中以禁用由配置指定的通信路径。 可以操作多处理器结构以根据配置执行软件应用。

公开(公告)号：US20120102299A1

公开(公告)日：2012-04-26

申请号：US13341252

申请日：2011-12-30

Applicant: Michael B. Doerr ,  William H. Hallidy ,  David A. Gibson ,  Craig M. Chase

Inventor： Michael B. Doerr ,  William H. Hallidy ,  David A. Gibson ,  Craig M. Chase

IPC: G06F15/76 ,  G06F9/06 ,  G06F15/80

CPC classification number: G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

Abstract translation: 处理系统包括处理器和以散置的布置耦合在一起的动态可配置通信元件（DCC）。 源设备可以通过DCC的中间子集将数据项传送到目的地设备。 源和目的地设备可以各自对应于不同的处理器，DCC或输入/输出设备，或者它们的混合组合。 响应于在源设备开始将数据项传送到目的地设备之后并且在接收到目的地设备之前的所有数据项之前检测到停顿，停顿设备可操作以通过一个或多个 中间子集朝向源设备。 响应于接收到停止信息，中间子集中的至少一个可操作以缓冲数据项的全部或部分。

公开(公告)号：US5253199A

公开(公告)日：1993-10-12

申请号：US717302

申请日：1991-06-17

Applicant: David A. Gibson

Inventor： David A. Gibson

IPC: G11C11/44

CPC classification number: G11C11/44

Abstract: Apparatus for selecting memory cells in a MOS memory array and reading data contained therein. Superconducting Josephson junction devices switch between a superconducting and voltage gap mode for rapid selection of an addressed memory cell row and column, and then read out of the selected memory cell data contained therein.

Abstract translation: 用于选择MOS存储器阵列中的存储器单元并读取其中包含的数据的装置。 超导约瑟夫逊结器件在超导和电压间隙模式之间切换，用于快速选择寻址的存储器单元行和列，然后读出其中包含的所选择的存储器单元数据。

公开(公告)号：US5227579A

公开(公告)日：1993-07-13

申请号：US896631

申请日：1992-06-10

Applicant: David A. Gibson ,  Charles S. Cornelius

Inventor： David A. Gibson ,  Charles S. Cornelius

IPC: B64G1/00 ,  B64G1/40 ,  B64G1/64 ,  F42B15/36

CPC classification number: F42B15/36 ,  B64G1/002 ,  B64G1/403 ,  B64G1/641 ,  B64G1/645

Abstract: The booster motors, each attached to and surrounding a centerbody, are mully connected to each other via one or more hollow manifold legs through which propulsive gases flow freely. At a predetermined time, the manifold cutter receives a signal activating the cutter to sever the manifold leg. Upon severance, the cut manifold leg still attached to the booster acts as a nozzle by venting residual propulsive gases and thereby propelling the booster away from the centerbody.

Abstract translation: 每个附接到中心体并围绕中心体的增压电动机通过一个或多个中空歧管支柱彼此相互连接，推进式气体可自由流动。 在预定时间，歧管切割器接收启动切割器以切断歧管腿的信号。 断裂时，仍然附着在增压器上的切割歧管腿通过排出残余的推进气体，从而将助推器推离中心体，作为喷嘴。

公开(公告)号：US08478964B2

公开(公告)日：2013-07-02

申请号：US13341252

申请日：2011-12-30

Applicant: Michael B. Doerr ,  William H. Hallidy ,  David A. Gibson ,  Craig M. Chase

Inventor： Michael B. Doerr ,  William H. Hallidy ,  David A. Gibson ,  Craig M. Chase

IPC: G06F9/00

CPC classification number: G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

Abstract translation: 处理系统包括处理器和以散置的布置耦合在一起的动态可配置通信元件（DCC）。 源设备可以通过DCC的中间子集将数据项传送到目的地设备。 源和目的地设备可以各自对应于不同的处理器，DCC或输入/输出设备，或者它们的混合组合。 响应于在源设备开始将数据项传送到目的地设备之后并且在接收到目的地设备之前的所有数据项之前检测到停顿，停顿设备可操作以通过一个或多个 中间子集朝向源设备。 响应于接收到停止信息，中间子集中的至少一个可操作以缓冲数据项的全部或部分。

公开(公告)号：US20100228925A1

公开(公告)日：2010-09-09

申请号：US12781314

申请日：2010-05-17

Applicant: Michael B. Doerr ,  William H. Hallidy ,  David A. Gibson ,  Craig M. Chase

Inventor： Michael B. Doerr ,  William H. Hallidy ,  David A. Gibson ,  Craig M. Chase

IPC: G06F15/80 ,  G06F9/06 ,  G06F12/00

CPC classification number: G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

Abstract: A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

Abstract translation: 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。

公开(公告)号：US06520729B1

公开(公告)日：2003-02-18

申请号：US09600601

申请日：2000-07-19

Applicant: David A. Gibson

Inventor： David A. Gibson

IPC: B65G6900

CPC classification number: B61D47/00 ,  B61D3/04 ,  B61D3/20 ,  B61D45/006

Abstract: Apparatus is provided for transporting a load from a source to a destination. The apparatus includes a freight container (1) which has a plurality of cells (7) each for containing a discrete load and a conveyor (10) for conveying loads between cells (7). Plural discrete loads are loaded into the container (1). The loads are allocated amongst the cells (7) according to the destinations of the individual loads and then each individual load is conveyed to its allocated cell (7).

Abstract translation: 提供了用于将负载从源运送到目的地的装置。 该装置包括货物容器（1），其具有多个用于容纳离散负载的单元（7）和用于在单元（7）之间传送载荷的输送机（10）。 多个离散的载荷被装载到容器（1）中。 根据各个负载的目的地，在单元（7）中分配负载，然后将每个单独的负载传送到其分配的单元（7）。

公开(公告)号：US06203049B1

公开(公告)日：2001-03-20

申请号：US09186978

申请日：1998-11-05

Applicant: David A. Gibson

Inventor： David A. Gibson

IPC: B60D1300

CPC classification number: B60D1/155 ,  A01B59/042 ,  B60D1/14 ,  B60D2001/548

Abstract: A terrain following hitch which mounts on a tractor draw bar by a pin, and which allows an implement being towed to move in three planes, independent of the tractor. The hitch includes three hinges, and a draw bar attachment tube which fits over the draw bar of a tractor, and transmits force to the walls of the draw bar, instead of into the pin and pin holes. The hitch reduces wear on implements and hitch connections.

Abstract translation: 一个地形跟随，挂在一个拖拉机拉杆通过一个销，并允许工具被牵引移动在三个平面，独立于拖拉机。 挂钩包括三个铰链，以及一个装配在拖拉机的牵引杆上的拉杆连接管，并且将力传递到拉杆的壁而不是销和销孔。 挂钩减少了工具和挂钩连接的磨损。

公开(公告)号：US20120137119A1

公开(公告)日：2012-05-31

申请号：US13274138

申请日：2011-10-14

Applicant: Michael B. Doerr ,  Carl S. Dobbs ,  Michael B. Solka ,  Michael R. Trocino ,  David A. Gibson

Inventor： Michael B. Doerr ,  Carl S. Dobbs ,  Michael B. Solka ,  Michael R. Trocino ,  David A. Gibson

IPC: G06F9/00

CPC classification number: G06F21/71 ,  G06F3/0635 ,  G06F9/4405 ,  G06F13/00 ,  G06F13/4221 ,  G06F15/163 ,  G06F15/167 ,  G06F15/17343 ,  G06F15/177 ,  G06F15/76 ,  G06F21/575 ,  G06F2221/034

Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.

Abstract translation: 禁用多处理器结构中的通信。 多处理器结构可以包括多个处理器和多个通信元件，并且多个通信元件中的每一个可以包括存储器。 可以为多处理器结构接收配置，其指定禁用以下中的一个或多个：一个或多个处理器和一个或多个通信元件之间的通信路径; 一个或多个处理器和一个或多个其他处理器; 或一个或多个通信元件和一个或多个其他通信元件。 因此，多处理器结构可以被自动地配置在硬件中以禁用由配置指定的通信路径。 可以操作多处理器结构以根据配置执行软件应用。

公开(公告)号：US07987339B2

公开(公告)日：2011-07-26

申请号：US12827416

申请日：2010-06-30

Applicant: Michael B. Doerr ,  William H. Hallidy ,  David A. Gibson ,  Craig M. Chase

Inventor： Michael B. Doerr ,  William H. Hallidy ,  David A. Gibson ,  Craig M. Chase

IPC: G06F15/76 ,  G06F15/80

CPC classification number: G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

Abstract: A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

Abstract translation: 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。