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    Multi-processor system with system wide reset and partial system reset capabilities
    4.
    发明授权
    Multi-processor system with system wide reset and partial system reset capabilities 失效
    具有系统复位和部分系统复位功能的多处理器系统

    公开(公告)号：US5870602A

    公开(公告)日：1999-02-09

    申请号：US14369

    申请日：1998-01-27

    申请人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley ,  Mark Taylor ,  Javier F. Izquierdo

    发明人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley ,  Mark Taylor ,  Javier F. Izquierdo

    IPC分类号： G06F1/24 ,  G06F9/00

    CPC分类号： G06F1/24

    摘要： A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. Each processing unit is reset in response to a system reset signal but only selected portions of the processing units are reset in response to a partial-reset signal. The system can also include a number other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

    摘要翻译： 多处理器系统包括第一和第二处理单元。 这些处理单元中的每一个至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。 每个处理单元响应于系统复位信号被复位，但只响应于部分复位信号来复位处理单元的选定部分。 该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

    Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration
    5.
    发明授权
    Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration 失效
    在单个处理器中具有较低优先级多处理器仲裁和较高优先级的两级系统总线仲裁以及多个总线主机仲裁

    公开(公告)号：US5392436A

    公开(公告)日：1995-02-21

    申请号：US249665

    申请日：1994-05-26

    申请人： Kenneth A. Jansen ,  Montgomery C. McGraw ,  David A. Miller ,  Paul R. Culley

    发明人： Kenneth A. Jansen ,  Montgomery C. McGraw ,  David A. Miller ,  Paul R. Culley

    IPC分类号： G06F13/362 ,  G06F13/36 ,  G06F13/18

    CPC分类号： G06F13/362

    摘要： A method and apparatus for arbitrating between multiple processors that can be incorporated into an arbitration scheme that is designed to include only a single processor. The method includes consolidating the individual bus requests of each processor into a single bus request supplied to the single processor arbitration scheme. When control of the bus is allocated to the single processor, the multiprocessor arbitration arbitrates among the processors who requested the bus. The bus protocol used includes a least recently used method for granting bus access to the multiple processors coupled with a means for giving one processor priority over the others for access to the bus. The protocol also includes protection from interruption for the respective processor in control of the bus for a preset period of time.

    摘要翻译： 一种用于在可被并入设计成仅包括单个处理器的仲裁方案中的多个处理器之间进行仲裁的方法和装置。 该方法包括将每个处理器的各个总线请求整合到提供给单处理器仲裁方案的单个总线请求中。 当总线的控制被分配给单个处理器时，多处理器仲裁在请求总线的处理器之间进行仲裁。 所使用的总线协议包括最近最少使用的用于授予对多个处理器的总线访问的方法，该方法与用于给予一个处理器优先级的方式相比，用于访问总线。 该协议还包括在预设时间段内控制总线的各个处理器的中断保护。

    Processor based system with system wide reset and partial system reset capabilities
    6.
    发明授权
    Processor based system with system wide reset and partial system reset capabilities 失效
    基于处理器的系统具有系统复位和部分系统复位功能

    公开(公告)号：US06463529B1

    公开(公告)日：2002-10-08

    申请号：US08797036

    申请日：1997-02-10

    申请人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley

    发明人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley

    IPC分类号： G06F124

    CPC分类号： G06F12/0802 ,  G06F1/24 ,  G06F15/177

    摘要： A processor-based system includes a processing unit. The processing unit includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. The processing unit is reset in response to a system reset signal being asserted at a reset input node and only selected portions of the processing unit are reset in response to a partial-reset signal being asserted at a partial-reset input node. The system can also include a number of other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

    摘要翻译： 基于处理器的系统包括处理单元。 处理单元至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。 处理单元响应于在复位输入节点断言的系统复位信号被复位，并且响应于部分复位输入节点断言的部分复位信号仅复位处理单元的选定部分。 该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

    Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals
    7.
    发明授权
    Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals 失效
    存储器访问系统，具有使用写保护和选通信号的接口和存储器选择单元

    公开(公告)号：US5341494A

    公开(公告)日：1994-08-23

    申请号：US165514

    申请日：1993-12-10

    申请人： John S. Thayer ,  Dale J. Mayer ,  Javier F. Izquierdo ,  Paul R. Culley ,  John A. Landry

    发明人： John S. Thayer ,  Dale J. Mayer ,  Javier F. Izquierdo ,  Paul R. Culley ,  John A. Landry

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0653

    摘要： A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

    摘要翻译： 存储器映射和模块使能电路，用于允许为连接到存储器系统的任何模块中的任何位置定义逻辑128K字节的存储器块。 RAM由定义128千字节块的系统地址线寻址，输出数据为特定存储器模块提供行地址选通使能信号，以及将128K字节块放置在模块内所需的地址值。 各种其他参数，如写保护状态和存储器位置也由RAM提供。 提供了用于编程和读取RAM的电路和技术。

    Double buffering operations between the memory bus and the expansion bus of a computer system
    8.
    发明授权
    Double buffering operations between the memory bus and the expansion bus of a computer system 失效

    公开(公告)号：US5870568A

    公开(公告)日：1999-02-09

    申请号：US903949

    申请日：1997-07-31

    申请人： Paul R. Culley ,  Mark Taylor

    发明人： Paul R. Culley ,  Mark Taylor

    IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F13/40 ,  G06F13/20

    CPC分类号： G06F13/1673 ,  G06F12/0215 ,  G06F13/4018

    摘要： Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.

    Double buffering operations between the memory bus and the expansion bus of a computer system
    9.
    发明授权
    Double buffering operations between the memory bus and the expansion bus of a computer system 失效

    公开(公告)号：US5519839A

    公开(公告)日：1996-05-21

    申请号：US956068

    申请日：1992-10-02

    申请人： Paul R. Culley ,  Mark Taylor

    发明人： Paul R. Culley ,  Mark Taylor

    IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F13/40 ,  G06F12/08

    CPC分类号： G06F13/1673 ,  G06F12/0215 ,  G06F13/4018

    摘要： Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.

    Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems
    10.
    发明授权
    Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems 失效
    多处理计算机系统中的微处理器的拆分事务和流水线仲裁

    公开(公告)号：US5553310A

    公开(公告)日：1996-09-03

    申请号：US955930

    申请日：1992-10-02

    申请人： Mark Taylor ,  Paul R. Culley ,  Maria L. Melo ,  Roger E. Tipley

    发明人： Mark Taylor ,  Paul R. Culley ,  Maria L. Melo ,  Roger E. Tipley

    IPC分类号： G06F13/364 ,  G06F13/14 ,  G06F13/18

    CPC分类号： G06F13/364

    摘要： Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

    摘要翻译： 用于确定几个CPU中的哪一个接收优先级以在多处理器系统中成为主机总线的总线主机的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制传输何时由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 分割事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被另一个设备控制，数据在空闲时也在主机总线上被断言。