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    Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration
    4.
    发明授权
    Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration 失效
    在单个处理器中具有较低优先级多处理器仲裁和较高优先级的两级系统总线仲裁以及多个总线主机仲裁

    公开(公告)号：US5392436A

    公开(公告)日：1995-02-21

    申请号：US249665

    申请日：1994-05-26

    申请人： Kenneth A. Jansen ,  Montgomery C. McGraw ,  David A. Miller ,  Paul R. Culley

    发明人： Kenneth A. Jansen ,  Montgomery C. McGraw ,  David A. Miller ,  Paul R. Culley

    IPC分类号： G06F13/362 ,  G06F13/36 ,  G06F13/18

    CPC分类号： G06F13/362

    摘要： A method and apparatus for arbitrating between multiple processors that can be incorporated into an arbitration scheme that is designed to include only a single processor. The method includes consolidating the individual bus requests of each processor into a single bus request supplied to the single processor arbitration scheme. When control of the bus is allocated to the single processor, the multiprocessor arbitration arbitrates among the processors who requested the bus. The bus protocol used includes a least recently used method for granting bus access to the multiple processors coupled with a means for giving one processor priority over the others for access to the bus. The protocol also includes protection from interruption for the respective processor in control of the bus for a preset period of time.

    摘要翻译： 一种用于在可被并入设计成仅包括单个处理器的仲裁方案中的多个处理器之间进行仲裁的方法和装置。 该方法包括将每个处理器的各个总线请求整合到提供给单处理器仲裁方案的单个总线请求中。 当总线的控制被分配给单个处理器时，多处理器仲裁在请求总线的处理器之间进行仲裁。 所使用的总线协议包括最近最少使用的用于授予对多个处理器的总线访问的方法，该方法与用于给予一个处理器优先级的方式相比，用于访问总线。 该协议还包括在预设时间段内控制总线的各个处理器的中断保护。

    Processor based system with system wide reset and partial system reset capabilities
    5.
    发明授权
    Processor based system with system wide reset and partial system reset capabilities 失效
    基于处理器的系统具有系统复位和部分系统复位功能

    公开(公告)号：US06463529B1

    公开(公告)日：2002-10-08

    申请号：US08797036

    申请日：1997-02-10

    申请人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley

    发明人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley

    IPC分类号： G06F124

    CPC分类号： G06F12/0802 ,  G06F1/24 ,  G06F15/177

    摘要： A processor-based system includes a processing unit. The processing unit includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. The processing unit is reset in response to a system reset signal being asserted at a reset input node and only selected portions of the processing unit are reset in response to a partial-reset signal being asserted at a partial-reset input node. The system can also include a number of other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

    摘要翻译： 基于处理器的系统包括处理单元。 处理单元至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。 处理单元响应于在复位输入节点断言的系统复位信号被复位，并且响应于部分复位输入节点断言的部分复位信号仅复位处理单元的选定部分。 该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

    Multi-processor system with system wide reset and partial system reset capabilities
    6.
    发明授权
    Multi-processor system with system wide reset and partial system reset capabilities 失效
    具有系统复位和部分系统复位功能的多处理器系统

    公开(公告)号：US5870602A

    公开(公告)日：1999-02-09

    申请号：US14369

    申请日：1998-01-27

    申请人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley ,  Mark Taylor ,  Javier F. Izquierdo

    发明人： David A. Miller ,  Kenneth A. Jansen ,  Paul R. Culley ,  Mark Taylor ,  Javier F. Izquierdo

    IPC分类号： G06F1/24 ,  G06F9/00

    CPC分类号： G06F1/24

    摘要： A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. Each processing unit is reset in response to a system reset signal but only selected portions of the processing units are reset in response to a partial-reset signal. The system can also include a number other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

    摘要翻译： 多处理器系统包括第一和第二处理单元。 这些处理单元中的每一个至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。 每个处理单元响应于系统复位信号被复位，但只响应于部分复位信号来复位处理单元的选定部分。 该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

    Method and apparatus for diagnosing fault states in a computer system
    10.
    发明授权
    Method and apparatus for diagnosing fault states in a computer system 失效
    用于诊断计算机系统中的故障状态的方法和装置

    公开(公告)号：US6000040A

    公开(公告)日：1999-12-07

    申请号：US739687

    申请日：1996-10-29

    申请人： Paul R. Culley ,  Joseph P. Miller ,  Daniel S. Hull ,  Siamak Tavallaei

    发明人： Paul R. Culley ,  Joseph P. Miller ,  Daniel S. Hull ,  Siamak Tavallaei

    IPC分类号： G06F11/22 ,  G06F11/07 ,  G06F11/00

    CPC分类号： G06F11/0745 ,  G06F11/0748 ,  G06F11/079

    摘要： Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines. One of the circuits includes an internal clock, and the fault state of the circuit includes the internal clock not functioning properly. One of the circuits includes a temperature sensor, and the fault state of the circuit includes a high temperature condition detected by the temperature sensor.

    摘要翻译： 具有电路的计算机系统中的故障由连接的故障检测器来管理，以检测各个电路的故障状态。 故障管理器将故障状态与相应的电路相关联。 故障管理器包括连接到系统管理器以识别哪些电路在计算机系统中导致故障的操作。 与相应电路相关联的故障检测器被配置为检测各个电路的故障操作并产生故障状态信息。 连接中央管理器，从故障检测器累积故障状态信息。 其中一个电路包括总线，故障状态包括总线错误状况。 总线连接到多个设备，故障管理器识别多个设备中的哪一个引起总线错误状况。 其中一个电路包括多个模块，故障管理器识别多个模块的故障状态。 模块包括状态机。 其中一个电路包括内部时钟，并且电路的故障状态包括内部时钟不能正常工作。 其中一个电路包括温度传感器，并且电路的故障状态包括由温度传感器检测的高温条件。