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公开(公告)号：US07730346B2
公开(公告)日：2010-06-01
申请号：US11742029
申请日：2007-04-30
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C29/44 , G11C29/76 , G11C2029/0411 , G11C2029/1208
摘要： A method includes storing a first data to a first portion of a storage location of a storage component of a processing device in association with a first store operation and obtaining a second data from the storage location, the second data being stored at the storage location prior to the first data. The method further includes determining whether the storage location has a bit error at second portion of the storage location different from the first portion based on the second data obtained from the storage location. The method additionally includes storing a third data to a second portion of the storage location in response to determining the storage location has a bit error at the second portion, wherein the third data is to correct the bit error.
摘要翻译： 一种方法包括将第一数据存储到与第一存储操作相关联的处理设备的存储部件的存储位置的第一部分，并从存储位置获取第二数据，第二数据存储在存储位置之前 到第一个数据。 该方法还包括基于从存储位置获得的第二数据来确定存储位置是否存在与第一部分不同的存储位置的第二部分处的位错误。 该方法还包括响应于确定存储位置在第二部分处具有位错误而将第三数据存储到存储位置的第二部分，其中第三数据用于校正位错误。
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公开(公告)号：US20080270824A1
公开(公告)日：2008-10-30
申请号：US11742029
申请日：2007-04-30
IPC分类号： G06F11/16
CPC分类号： G06F11/1048 , G11C29/44 , G11C29/76 , G11C2029/0411 , G11C2029/1208
摘要： A method includes storing a first data to a first portion of a storage location of a storage component of a processing device in association with a first store operation and obtaining a second data from the storage location, the second data being stored at the storage location prior to the first data. The method further includes determining whether the storage location has a bit error at second portion of the storage location different from the first portion based on the second data obtained from the storage location. The method additionally includes storing a third data to a second portion of the storage location in response to determining the storage location has a bit error at the second portion, wherein the third data is to correct the bit error.
摘要翻译： 一种方法包括将第一数据存储到与第一存储操作相关联的处理设备的存储部件的存储位置的第一部分，并从存储位置获取第二数据，第二数据存储在存储位置之前 到第一个数据。 该方法还包括基于从存储位置获得的第二数据来确定存储位置是否存在与第一部分不同的存储位置的第二部分处的位错误。 该方法还包括响应于确定存储位置在第二部分处具有位错误而将第三数据存储到存储位置的第二部分，其中第三数据用于校正位错误。
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公开(公告)号：US08583894B2
公开(公告)日：2013-11-12
申请号：US12878513
申请日：2010-09-09
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026 , Y02D10/13
摘要： A hybrid prefetch method and apparatus is disclosed. A processor includes a hybrid prefetch unit configured to generate addresses for accessing data from a system memory. The hybrid prefetch unit includes a first prediction unit configured to generate a first memory address according to a first prefetch algorithm and a second prediction unit configured to generate a second memory address according to a second prefetch algorithm. The hybrid prefetcher further includes an arbitration unit configured to select one of the first and second memory addresses and further configured to provide the selected one of the first and second memory addresses during a prefetch operation.
摘要翻译： 公开了一种混合预取方法和装置。 处理器包括配置成生成用于从系统存储器访问数据的地址的混合预取单元。 混合预取单元包括：第一预测单元，被配置为根据第一预取算法生成第一存储器地址;第二预测单元，被配置为根据第二预取算法生成第二存储器地址。 混合预取器还包括仲裁单元，其被配置为选择第一和第二存储器地址中的一个，并且还被配置为在预取操作期间提供所选择的第一和第二存储器地址之一。
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公开(公告)号：US07389402B2
公开(公告)日：2008-06-17
申请号：US11146863
申请日：2005-06-07
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/681
摘要： A translation lookaside buffer may include control functionality coupled to a first storage and a second storage. The first storage includes a first plurality of entries for storing address translations corresponding to a plurality of page sizes. The second storage includes a second plurality of entries for storing address translations corresponding to the plurality of page sizes. In response to receiving a first address translation associated with a first page size, the control functionality may allocate the first plurality of entries to store address translations corresponding to the first page size. In addition, in response to receiving a request including an address that matches an address translation stored within the first storage, the control functionality may copy a matching address translation from the first storage to the second storage.
摘要翻译： 翻译后备缓冲器可以包括耦合到第一存储器和第二存储器的控制功能。 第一存储器包括用于存储对应于多个页面大小的地址转换的第一多个条目。 第二存储器包括用于存储对应于多个页面大小的地址转换的第二多个条目。 响应于接收到与第一页大小相关联的第一地址转换，控制功能可以分配第一多个条目以存储对应于第一页大小的地址转换。 此外，响应于接收到包括与存储在第一存储器中的地址转换相匹配的地址的请求，控制功能可以将匹配的地址转换从第一存储复制到第二存储。
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公开(公告)号：US20060277390A1
公开(公告)日：2006-12-07
申请号：US11146863
申请日：2005-06-07
申请人： Gerald Zuraski , Swamy Punyamurtula
发明人： Gerald Zuraski , Swamy Punyamurtula
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/681
摘要： A translation lookaside buffer may include control functionality coupled to a first storage and a second storage. The first storage includes a first plurality of entries for storing address translations corresponding to a plurality of page sizes. The second storage includes a second plurality of entries for storing address translations corresponding to the plurality of page sizes. In response to receiving a first address translation associated with a first page size, the control functionality may allocate the first plurality of entries to store address translations corresponding to the first page size. In addition, in response to receiving a request including an address that matches an address translation stored within the first storage, the control functionality may copy a matching address translation from the first storage to the second storage.
摘要翻译： 翻译后备缓冲器可以包括耦合到第一存储器和第二存储器的控制功能。 第一存储器包括用于存储对应于多个页面大小的地址转换的第一多个条目。 第二存储器包括用于存储对应于多个页面大小的地址转换的第二多个条目。 响应于接收到与第一页大小相关联的第一地址转换，控制功能可以分配第一多个条目以存储对应于第一页大小的地址转换。 此外，响应于接收到包括与存储在第一存储器中的地址转换相匹配的地址的请求，控制功能可以将匹配的地址转换从第一存储复制到第二存储。
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公开(公告)号：US20120131305A1
公开(公告)日：2012-05-24
申请号：US12951567
申请日：2010-11-22
申请人： Swamy Punyamurtula
发明人： Swamy Punyamurtula
IPC分类号： G06F12/10
CPC分类号： G06F12/0862
摘要： A processor includes a prefetch aware prefetch unit having a storage with a number of entries, and each entry corresponds to a different prefetch data stream. Each entry may be configured to store information corresponding to a page size of the prefetch data stream, along with, for example, an address corresponding to the prefetch data stream. For each entry, the prefetch unit may be configured to determine whether a prefetch of data in the data stream will cross a page boundary associated with the data stream based upon the page size information.
摘要翻译： 处理器包括具有多个条目的存储器的预取感知预取单元，并且每个条目对应于不同的预取数据流。 每个条目可以被配置为存储对应于预取数据流的页面大小的信息，以及例如与预取数据流相对应的地址。 对于每个条目，预取单元可以被配置为基于页面大小信息来确定数据流中的数据预取是否将跨越与数据流相关联的页面边界。
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公开(公告)号：US20120066455A1
公开(公告)日：2012-03-15
申请号：US12878513
申请日：2010-09-09
CPC分类号： G06F12/0862 , G06F2212/6026 , Y02D10/13
摘要： A hybrid prefetch method and apparatus is disclosed. A processor includes a hybrid prefetch unit configured to generate addresses for accessing data from a system memory. The hybrid prefetch unit includes a first prediction unit configured to generate a first memory address according to a first prefetch algorithm and a second prediction unit configured to generate a second memory address according to a second prefetch algorithm. The hybrid prefetcher further includes an arbitration unit configured to select one of the first and second memory addresses and further configured to provide the selected one of the first and second memory addresses during a prefetch operation.
摘要翻译： 公开了一种混合预取方法和装置。 处理器包括配置成生成用于从系统存储器访问数据的地址的混合预取单元。 混合预取单元包括：第一预测单元，被配置为根据第一预取算法生成第一存储器地址;第二预测单元，被配置为根据第二预取算法生成第二存储器地址。 混合预取器还包括仲裁单元，其被配置为选择第一和第二存储器地址中的一个，并且还被配置为在预取操作期间提供所选择的第一和第二存储器地址之一。
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公开(公告)号：US20110066811A1
公开(公告)日：2011-03-17
申请号：US12558465
申请日：2009-09-11
CPC分类号： G06F12/0862 , G06F12/0815 , G06F2212/6026
摘要： A system and method for efficient data prefetching. A data stream stored in lower-level memory comprises a contiguous block of data used in a computer program. A prefetch unit in a processor detects a data stream by identifying a sequence of storage accesses referencing a contiguous blocks of data in a monotonically increasing or decreasing manner. After a predetermined training period for a given data stream, the prefetch unit prefetches a portion of the given data stream from memory without write permission, in response to an access that does not request write permission. Also, after the training period, the prefetch unit prefetches a portion of the given data stream from lower-level memory with write permission, in response to determining there has been a prior access to the given data stream that requests write permission subsequent to a number of cache misses reaching a predetermined threshold.
摘要翻译： 一种用于高效数据预取的系统和方法。 存储在下级存储器中的数据流包括在计算机程序中使用的连续的数据块。 处理器中的预取单元通过以单调递增或递减的方式识别参考连续数据块的存储访问序列来检测数据流。 在针对给定数据流的预定训练周期之后，响应于不请求写许可的访问，预取单元从存储器中预取给定数据流的一部分而不具有写许可。 此外，在训练期之后，预取单元响应于确定先前访问给定数据流的请求后的写入权限，从而从具有写许可的下级存储器中预取给定数据流的一部分 的高速缓存未命中达到预定阈值。
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公开(公告)号：US08667225B2
公开(公告)日：2014-03-04
申请号：US12558465
申请日：2009-09-11
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0815 , G06F2212/6026
摘要： A system and method for efficient data prefetching. A data stream stored in lower-level memory comprises a contiguous block of data used in a computer program. A prefetch unit in a processor detects a data stream by identifying a sequence of storage accesses referencing a contiguous blocks of data in a monotonically increasing or decreasing manner. After a predetermined training period for a given data stream, the prefetch unit prefetches a portion of the given data stream from memory without write permission, in response to an access that does not request write permission. Also, after the training period, the prefetch unit prefetches a portion of the given data stream from lower-level memory with write permission, in response to determining there has been a prior access to the given data stream that requests write permission subsequent to a number of cache misses reaching a predetermined threshold.
摘要翻译： 一种用于高效数据预取的系统和方法。 存储在下级存储器中的数据流包括在计算机程序中使用的连续的数据块。 处理器中的预取单元通过以单调递增或递减的方式识别参考连续数据块的存储访问序列来检测数据流。 在针对给定数据流的预定训练周期之后，响应于不请求写许可的访问，预取单元从存储器中预取给定数据流的一部分而不具有写许可。 此外，在训练期之后，预取单元响应于确定先前访问给定数据流的请求后的写入权限，从而从具有写许可的下级存储器中预取给定数据流的一部分 的高速缓存未命中达到预定阈值。
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