-
公开(公告)号：US07389402B2
公开(公告)日：2008-06-17
申请号：US11146863
申请日：2005-06-07
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/681
摘要： A translation lookaside buffer may include control functionality coupled to a first storage and a second storage. The first storage includes a first plurality of entries for storing address translations corresponding to a plurality of page sizes. The second storage includes a second plurality of entries for storing address translations corresponding to the plurality of page sizes. In response to receiving a first address translation associated with a first page size, the control functionality may allocate the first plurality of entries to store address translations corresponding to the first page size. In addition, in response to receiving a request including an address that matches an address translation stored within the first storage, the control functionality may copy a matching address translation from the first storage to the second storage.
摘要翻译： 翻译后备缓冲器可以包括耦合到第一存储器和第二存储器的控制功能。 第一存储器包括用于存储对应于多个页面大小的地址转换的第一多个条目。 第二存储器包括用于存储对应于多个页面大小的地址转换的第二多个条目。 响应于接收到与第一页大小相关联的第一地址转换，控制功能可以分配第一多个条目以存储对应于第一页大小的地址转换。 此外，响应于接收到包括与存储在第一存储器中的地址转换相匹配的地址的请求，控制功能可以将匹配的地址转换从第一存储复制到第二存储。
-
2.发明授权公开(公告)号：US08181005B2
公开(公告)日：2012-05-15
申请号：US12205429
申请日：2008-09-05
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an i-cache line comprises additional branches, the device stores the corresponding branch prediction information in a dense cache. Each entry of the sparse cache stores a bit vector indicating whether or not a corresponding instruction cache line includes additional branch instructions. This indication may also be used to select an entry in the dense cache for storage. A second sparse cache stores entire evicted entries from the first sparse cache.
摘要翻译： 一种用于微处理器中分支预测的系统和方法。 混合设备将稀疏高速缓存中的分支预测信息存储在指令高速缓存的每个条目内不超过公共较小数量的分支。 对于i-cache行包括附加分支的较不常见的情况，该设备将相应的分支预测信息存储在密集高速缓存中。 稀疏高速缓存的每个条目存储指示对应的指令高速缓存行是否包括附加分支指令的位向量。 此指示也可用于选择密集缓存中的条目以进行存储。 第二个稀疏缓存存储从第一个稀疏高速缓存中的所有被驱逐的条目。
-
3.发明授权Method and processor including logic for storing traces within a trace cache 有权方法和处理器包括用于在跟踪高速缓存中存储轨迹的逻辑公开(公告)号：US07213126B1
公开(公告)日：2007-05-01
申请号：US10755742
申请日：2004-01-12
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/3806 , G06F9/3808 , G06F9/382 , G06F12/0875
摘要： A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be associated with a respective address. The trace cache memory is coupled to the trace generator and includes a plurality of entries each configured to store one of the traces. The trace generator may be further configured to restrict each of the traces to include only operations having respective addresses that fall within one or more predetermined ranges of contiguous addresses.
摘要翻译： 处理器包括耦合到跟踪发生器的跟踪高速缓冲存储器。 跟踪发生器可以被配置为生成多个迹线，每个迹线包括可以从一个或多个指令解码的一个或多个操作。 每个操作可以与相应的地址相关联。 跟踪高速缓存存储器耦合到跟踪生成器，并且包括多个条目，每个条目被配置为存储跟踪的一个。 跟踪发生器还可以被配置为限制每个迹线仅包括具有落在连续地址的一个或多个预定范围内的相应地址的操作。
-
公开(公告)号：US06873184B1
公开(公告)日：2005-03-29
申请号：US10653802
申请日：2003-09-03
CPC分类号： G06F5/10 , G06F12/0862 , G06F2205/106
摘要： An apparatus comprises a buffer comprising a plurality of entries, an insert pointer, a delete pointer, a plurality of first control circuits coupled to the buffer, and a second control circuit coupled to the buffer. The entries are logically divided into a plurality of groups. Each of the first control circuits corresponds to a respective group and selects an entry from the respective group for potential reading from the buffer. Furthermore, each of the first control circuits, in the event that the delete pointer indicates a first entry in the respective group and the insert pointer wraps around the buffer and indicates a second entry in the respective group, selects the first entry if the first entry is eligible for selection. The second control circuit selects a first group, and the entry selected from the first group by the first control circuits is the entry read from the buffer.
摘要翻译： 一种装置包括缓冲器，该缓冲器包括多个条目，插入指针，删除指针，耦合到缓冲器的多个第一控制电路以及耦合到缓冲器的第二控制电路。 这些条目在逻辑上分为多个组。 每个第一控制电路对应于相应的组，并从相应组中选择一个来自缓冲器的电位读取的条目。 此外，在删除指针指示相应组中的第一条目并且插入指针围绕缓冲器包围并指示相应组中的第二条目的情况下，每个第一控制电路选择第一条目，如果第一条目 有资格选择。 第二控制电路选择第一组，并且由第一控制电路从第一组中选择的条目是从缓冲器读取的条目。
-
5.发明授权公开(公告)号：US06260134B1
公开(公告)日：2001-07-10
申请号：US09184750
申请日：1998-11-02
IPC分类号： G06F938
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816
摘要： A predecode unit is configured to predecode a fixed number of instruction bytes of variable length instructions per clock cycle. The predecode unit outputs predecode bits which identify the start byte of an instruction. An instruction alignment unit uses the start bits to dispatch the instructions to a plurality of decode units that form fixed issue positions. In one embodiment, the predecode unit identifies a plurality of length vectors. Each length vector is associated with one of the instruction bytes predecoded in a clock cycle and identifies the length of an instruction if an instruction starts at the instruction byte corresponding to the length vector. A tree circuit determines in which instruction bytes instructions start.
摘要翻译： 预解码单元被配置为对每个时钟周期的固定数量的可变长度指令的指令字节进行预解码。 预解码单元输出识别指令的起始字节的预解码位。 指令对准单元使用起始位将指令分派到形成固定发行位置的多个解码单元。 在一个实施例中，预解码单元识别多个长度向量。 每个长度向量与在时钟周期中预解码的指令字节之一相关联，并且如果指令在与长度向量相对应的指令字节处开始指示，则识别指令的长度。 树电路确定哪个指令字节指令开始。
-
6.发明授权Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor 失效用于检测在微处理器的指令处理流水线内的指令更新的方法
公开(公告)号：US6073217A
公开(公告)日：2000-06-06
申请号：US15087
申请日：1998-01-29
CPC分类号： G06F9/3812
摘要： A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction processing pipeline). Addresses corresponding to memory locations being modified are compared to the addresses stored in the core snoop buffer on a page basis. If a match is detected, then instructions are flushed from the instruction processing pipeline and refetched. In this manner, the instructions executed to the point of modifying registers or memory are correct in self-modifying code or multiprocessor environments. Instructions may be speculatively fetched and executed while retaining coherency with respect to changes to memory. The number of pages from which instructions are concurrently outstanding within the microprocessor are typically small compared to the number of cache lines outstanding or the number of instructions outstanding. Therefore, a relatively small hardware structure may be employed to perform the instruction coherency functionality.
摘要翻译： 提供了一种核心窥探缓冲装置，其存储已经从中取出指令但尚未退出的页面的地址（即指令在指令处理流水线内是突出的）。 对应于要修改的存储器位置的地址与基于页面的核心监听缓冲器中存储的地址进行比较。 如果检测到匹配，则从指令处理流水线刷新指令并进行重写。 以这种方式，执行到修改寄存器或存储器的指令的指令在自修改代码或多处理器环境中是正确的。 可以推测性地获取和执行指令，同时保留与内存更改相关的一致性。 相对于未完成的高速缓存线的数量或未完成的指令的数量，在微处理器内同时发生指令的页面的数量通常很小。 因此，可以采用相对小的硬件结构来执行指令一致性功能。
-
公开(公告)号：US5590352A
公开(公告)日：1996-12-31
申请号：US233567
申请日：1994-04-26
CPC分类号： G06F9/30043 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/30192 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A pipelined or superscalar processor (10) that executes operations utilizing operand data of variable bit widths improves parallel performance by partitioning a fixed bit width operand (200) into several partial operand fields (215, 216 and 217), and checking for data dependencies, tagging and forwarding data in these fields independently of one another. An instruction decoder (18) concurrently dispatches multiple ROPs to various functional units (20, 21, 22 and 80). Conflicts which arise with respect to register resources are resolved through register renaming. However, implementation of register renaming is difficult when register structures are overlapping. The present invention supports independent dependency checking, tagging and forwarding of partial bit fields of a register operand which, in combination, allow renaming of registers. Therefore, the variable width register operand structure greatly assists the processor to resolve data dependencies. Operands are tagged by a reorder buffer (26) and supplied with data when it becomes available without regard for the type of data. This method of dependency resolution supports parallel performance of operations and provides a substantial improvement in overall speed of processing. Thus, the processor promotes parallel processing of operations that act upon overlapping data structures which otherwise resist parallel handling.
摘要翻译： 使用可变位宽的操作数数据执行操作的流水线或超标量处理器（10）通过将固定位宽操作数（200）划分成几个部分操作数字段（215,216和217）来提高并行性能，并且检查数据依赖性， 在这些字段中标记和转发数据，彼此独立。 指令解码器（18）同时将多个ROP调度到各种功能单元（20,21,22和80）。 通过注册重命名来解决与注册资源有关的冲突。 然而，当寄存器结构重叠时，实现寄存器重命名是困难的。 本发明支持对寄存器操作数的部分位字段的独立依赖性检查，标记和转发，其组合允许寄存器重命名。 因此，可变宽度寄存器操作数结构大大有助于处理器解决数据依赖性。 操作数由重排序缓冲器（26）标记，并在数据可用时提供数据，而不考虑数据类型。 这种依赖关系的方法支持并行的操作性能，并提供整体处理速度的实质性改进。 因此，处理器促进对重叠的数据结构起作用的操作的并行处理，否则其将抵抗并行处理。
-
公开(公告)号：US07350119B1
公开(公告)日：2008-03-25
申请号：US10859284
申请日：2004-06-02
CPC分类号： G11C29/44 , G06F12/0802 , G11C29/4401 , G11C29/802 , G11C2029/0401
摘要： A hierarchical encoding format for coding repairs to devices within a computing system. A device, such as a cache memory, is logically partitioned into a plurality of sub-portions. Various portions of the sub-portions are identifiable as different levels of hierarchy of the device. A first sub-portion may corresponds to a particular cache, a second sub-portion may correspond to a particular way of the cache, and so on. The encoding format comprises a series of bits with a first portion corresponding to a first level of the hierarchy, and a second portion of the bits corresponds to a second level of the hierarchy. Each of the first and second portions of bits are preceded by a different valued bit which serves to identify the hierarchy to which the following bits correspond. A sequence of repairs are encoded as string of bits. The bit which follows a complete repair encoding indicates whether a repair to the currently identified cache is indicated or whether a new cache is targeted by the following repair. Therefore, certain repairs may be encoded without respecifying the entire hierarchy.
摘要翻译： 用于对维修计算系统内的设备进行编码的分层编码格式。 诸如高速缓冲存储器的设备被逻辑地分割成多个子部分。 子部分的各个部分可被识别为设备的不同层级。 第一子部分可以对应于特定高速缓存，第二子部分可以对应于高速缓存的特定方式，等等。 编码格式包括一系列位，其中第一部分对应于层级的第一级，并且位的第二部分对应于层级的第二级。 位的第一和第二部分中的每一个前面都有一个不同的值，用于识别跟随位对应的层级。 维修序列被编码为位串。 遵循完整修复编码的位指示是否指示对当前标识的高速缓存的修复，或者是否通过以下修复来定位新的高速缓存。 因此，可以编码某些修复，而不需要重新整理层次结构。
-
9.发明授权Apparatus and method for programmable built-in self-test and self-repair of embedded memory 有权嵌入式内存可编程内置自检和自修复的装置和方法公开(公告)号：US06560740B1
公开(公告)日：2003-05-06
申请号：US09366444
申请日：1999-08-03
IPC分类号： G01R3128
CPC分类号： G11C29/36 , G01R31/3187 , G11C29/16 , G11C29/846 , G11C2029/3202 , G11C2207/104
摘要： An apparatus and method are presented for programmable built-in self-test (BIST) and built-in self-repair (BISR) of an embedded memory (i.e., a memory formed with random logic upon a semiconductor substrate). A semiconductor device may include a memory unit, a BIST logic unit coupled to the memory unit, and a master test unit coupled to the BIST logic unit and the memory unit. The memory unit stores data input signals in response to a first set of address and control signals, and provides the stored data input signals as data output signals in response to a second set of address and control signals. The master test unit provides the memory test pattern to the BIST logic unit and generates the first and second sets of address and control signals. The BIST logic unit stores the memory test pattern, produces the data input signals dependent upon the memory test pattern, provides the data input signals to the memory unit, receives the data output signals from the memory unit, and compares the data output signals to the data input signals to form BIST results. The BIST system may perform a hardwired BIST routine when an asserted RESET signal is received by the semiconductor device and/or a programmable BIST routine under software control. The BIST logic unit may include a redundant memory structure, and may be configured to functionally replace a defective memory structure of the memory unit with one of the redundant memory structures dependent upon the BIST results.
摘要翻译： 提出了一种用于嵌入式存储器（即，在半导体衬底上形成有随机逻辑的存储器）的可编程内置自检（BIST）和内置自修复（BISR）的装置和方法。 半导体器件可以包括存储器单元，耦合到存储器单元的BIST逻辑单元和耦合到BIST逻辑单元和存储器单元的主测试单元。 存储单元响应于第一组地址和控制信号存储数据输入信号，并且响应于第二组地址和控制信号将存储的数据输入信号提供为数据输出信号。 主测试单元向BIST逻辑单元提供存储器测试模式，并产生第一组和第二组地址和控制信号。 BIST逻辑单元存储存储器测试模式，产生取决于存储器测试模式的数据输入信号，将数据输入信号提供给存储器单元，从存储器单元接收数据输出信号，并将数据输出信号与 数据输入信号形成BIST结果。 当由半导体器件接收到断言的RESET信号和/或软件控制下的可编程BIST例程时，BIST系统可以执行硬连线BIST程序。 BIST逻辑单元可以包括冗余存储器结构，并且可以被配置为使用依赖于BIST结果的冗余存储器结构之一来功能地替换存储器单元的有缺陷的存储器结构。
-
10.发明授权Dynamic classification of conditional branches in global history branch prediction 有权全球历史分支预测中条件分支的动态分类公开(公告)号：US06502188B1
公开(公告)日：2002-12-31
申请号：US09441630
申请日：1999-11-16
IPC分类号： G06F940
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/4486
摘要： A branch prediction unit includes a local branch prediction and a global branch prediction. A global branch prediction utilizes a global history shift register to record the behavior of conditional branches. In some cases, a conditional branch may behave in a static manner, either always being taken or not taken, while resident in an instruction cache. Such static behaving conditional branches do not need a global history for prediction and contend with other conditional branches for global branch history training. By utilizing a dynamic branch classification scheme, branches requiring global history prediction can be identified and static behaving conditional branches may be prevented from polluting the global history. All conditional branches are initially classified as local and do not participate in global history training. Only after two mispredictions are branches recognized as exhibiting dynamic behavior and classified as global. These branches classified as global may then participate in global history training and utilize a global history based branch prediction.
摘要翻译： 分支预测单元包括本地分支预测和全局分支预测。 全局分支预测利用全局历史移位寄存器来记录条件分支的行为。 在某些情况下，条件分支可以以静态方式表现，或者始终被采取或不占用，而驻留在指令高速缓存中。 这种静态行为条件分支不需要全球预测历史，并与其他条件分支进行全球分支历史训练。 通过使用动态分支分类方案，可以识别需要全局历史预测的分支，并且可以防止静态行为条件分支污染全球历史。 所有有条件的分支最初被分类为地方，不参加全球历史训练。 只有经过两次误解，分支机构被认为是表现出动态行为，被列为全球性的。 这些分类为全球的分支可以参与全球历史培训，并利用全球历史分支预测。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.022 秒)
