公开(公告)号：US06826100B2

公开(公告)日：2004-11-30

申请号：US10404405

申请日：2003-03-31

申请人： David G. Ellis ,  Bruce Querbach ,  Jay J. Nejedlo ,  Amjad Khan ,  Sean R. Babcock ,  Eric S. Gayles ,  Eshwar Gollapudi

发明人： David G. Ellis ,  Bruce Querbach ,  Jay J. Nejedlo ,  Amjad Khan ,  Sean R. Babcock ,  Eric S. Gayles ,  Eshwar Gollapudi

IPC分类号： G11C700

CPC分类号： G01R31/2853 ,  G01R31/31855 ,  G01R31/3187 ,  G06F11/27

摘要： A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

公开(公告)号：US07139957B2

公开(公告)日：2006-11-21

申请号：US10611099

申请日：2003-06-30

申请人： Bruce Querbach ,  David G. Ellis ,  Amjad Khan ,  Michael J. Tripp ,  Eric S. Gayles ,  Eshwar Gollapudi

发明人： Bruce Querbach ,  David G. Ellis ,  Amjad Khan ,  Michael J. Tripp ,  Eric S. Gayles ,  Eshwar Gollapudi

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： G06F11/27 ,  G01R31/31716 ,  G01R31/31853

摘要： A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

摘要翻译： 将多位测试值加载到IC组件的内置锁存器中，并选择组件的焊盘进行测试。 基于所存储的测试值，自动地生成许多不同的测试值序列，而不将附加的多位值扫描到锁存器中。 基于测试值的不同序列的信号被驱动到所选择的垫中并循环。 确定测试值和循环版测试值之间的差异，同时自动调整驱动器和/或接收器特性，以确定所选焊盘的片上I / O缓冲的操作余量。

公开(公告)号：US6078196A

公开(公告)日：2000-06-20

申请号：US932751

申请日：1997-09-17

申请人： Eric S. Gayles

发明人： Eric S. Gayles

IPC分类号： H03K19/096 ,  H03K19/173 ,  H03K19/094 ,  H03K19/00 ,  H03K19/20

CPC分类号： H03K19/1733 ,  H03K19/0963

摘要： Data enabled complex logic gates provide improved speed/power performance over conventional topologies such as static logic or clocked domino logic. Within a data enabled complex logic gate, complementary parallel logic structures, such as NFET logic trees, are configured such that for any combination of input variables one logic structure will produce a logic low as an output and the other logic structure will produce a logic high as an output. The logic structures are cross-coupled to each other by way of internal precharge devices, and are further individually coupled to an output latch. In this way the logic structures can be precharged to prepare for evaluation of the next set of input signals while the output latch maintains the result of the previous evaluation. In a further aspect of the invention, data enabled complex logic gates are combined with pass gate latches and multiplexer based logic gates to produce a high-speed, low-power logic pipeline.

摘要翻译： 数据启用的复杂逻辑门提供了比常规拓扑（例如静态逻辑或时钟多米诺逻辑）更高的速度/功率性能。 在启用数据的复杂逻辑门中，配置了诸如NFET逻辑树之类的互补并行逻辑结构，使得对于输入变量的任何组合，一个逻辑结构将产生作为输出的逻辑低，而另一逻辑结构将产生逻辑高 作为输出。 逻辑结构通过内部预充电装置彼此交叉耦合，并进一步单独地耦合到输出锁存器。 以这种方式，逻辑结构可以被预先充电以准备评估下一组输入信号，同时输出锁存器保持先前评估的结果。 在本发明的另一方面，数据使能的复杂逻辑门与传输门锁存器和基于复用器的逻辑门相结合以产生高速，低功率逻辑管线。

公开(公告)号：US5977789A

公开(公告)日：1999-11-02

申请号：US918975

申请日：1997-08-27

申请人： Eric S. Gayles

发明人： Eric S. Gayles

IPC分类号： H03K19/017 ,  H03K19/096

CPC分类号： H03K19/0963 ,  H03K19/01728

摘要： A logic device that allows the implementation of a fast-switching logic gate is described. One implementation of the logic device includes an output node and a reference node electrically isolated from one another by a transmission gate. During a first period of time, the nodes are charged to complementary logic levels. During a second period of time, the transmission gate is enabled, allowing the charge on the nodes to be redistributed. A pair of complementary input terminals are connected to the reference and output nodes, such that if the input terminal connected to the output node is at the same logic level as the output node during the first period, then the voltage level of the output node is pulled back from its redistributed state to its original state. However, if the input terminal voltage level to the output node is the complement of the original voltage level of the output node, then a charge/discharge circuit is enabled to pull the output node to a voltage level that is a complement to its original voltage level.

摘要翻译： 描述了允许实现快速切换逻辑门的逻辑器件。 逻辑器件的一个实施方式包括输出节点和通过传输门彼此电隔离的参考节点。 在第一时间段期间，节点被充电到互补逻辑电平。 在第二时间段期间，传输门被使能，允许节点上的电荷被重新分配。 一对互补输入端子连接到参考和输出节点，使得如果连接到输出节点的输入端在第一周期内与输出节点处于相同的逻辑电平，则输出节点的电压电平为 从其重新分配状态撤回到其原始状态。 然而，如果输出节点的输入端电压电平是输出节点的原始电压电平的补数，则使充电/放电电路能够将输出节点拉至与其原始电压互补的电压电平 水平。