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8 条记录 (耗时 0.024 秒)

    Multiple tier array capacitor
    1.
    发明授权
    Multiple tier array capacitor 有权
    多层阵列电容

    公开(公告)号：US06532143B2

    公开(公告)日：2003-03-11

    申请号：US09751612

    申请日：2000-12-29

    申请人： David G. Figueroa ,  Kishore K. Chakravorty ,  Huong T. Do ,  Larry Eugene Mosley ,  Jorge Pedro Rodriguez ,  Ken Brown

    发明人： David G. Figueroa ,  Kishore K. Chakravorty ,  Huong T. Do ,  Larry Eugene Mosley ,  Jorge Pedro Rodriguez ,  Ken Brown

    IPC分类号： H01G430

    CPC分类号： H01G4/30 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0298 ,  H05K1/162 ,  H01L2224/0401

    摘要： A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material. The capacitors of the various embodiments can be used as discrete devices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricated within the housing.

    摘要翻译： 电容器包括多层（302,304,306,1210,1212,1310,1312,1380，图3,12,13），其以不同的电感值向负载提供电容。 每个层包括被介电材料层隔开的图案化导电材料的多层（311-325,1220,1222,1320,1322,1382，图3,12,13）。 在一个实施例中，层是沿垂直方向堆叠的，并且通过延伸穿过一些或所有层的通孔（330,332,334,1230,1232，图3,12）电连接。 在另一个实施例中，一个或多个层（1310,1312，图13）位于电容器的中心区域（1404，图14）中，并且一个或多个其他层（图13中的1380）位于 电容器的外围区域（1408，图14）。 在该实施例中，中心层和外围层通过图案化导电材料的一个或多个附加层（1370，图13）电连接。 各种实施例的电容器可以用作可安装在壳体（例如，封装，插入件，插座或PC板）中或嵌入其中的分立器件，或者它们可以一体地制造在壳体内。

    Multi-layer chip capacitor
    2.
    发明授权
    Multi-layer chip capacitor 有权
    多层片式电容器

    公开(公告)号：US06724611B1

    公开(公告)日：2004-04-20

    申请号：US09537274

    申请日：2000-03-29

    申请人： Larry Eugene Mosley

    发明人： Larry Eugene Mosley

    IPC分类号： H01G4228

    CPC分类号： H01G4/33 ,  H01G4/228 ,  H01L27/016

    摘要： An integrated circuit thin film capacitor includes multiple layers of conductors separated by dielectric material. The conductive layers are connected to interconnect lands using conductive vias. The interconnect lands can be controlled collapse chip connection (C4) lands that allow the capacitor to be connected to a circuit board. In one embodiment, the capacitor is mounted on a circuit board in close proximity to a processor circuit. The multi layer capacitor of the present invention provides the ability to increase a capacitance value while lowering interconnect resistance and inductance.

    摘要翻译： 集成电路薄膜电容器包括由电介质材料隔开的多层导体。 使用导电通孔将导电层连接到互连焊盘。 可以将互连焊盘控制为允许电容器连接到电路板的崩溃芯片连接（C4）焊盘。 在一个实施例中，电容器安装在靠近处理器电路的电路板上。 本发明的多层电容器提供了在降低互连电阻和电感的同时增加电容值的能力。

    Supply voltage regulation system for transmission lines
    3.
    发明授权
    Supply voltage regulation system for transmission lines 失效
    输电线路供电电压调节系统

    公开(公告)号：US06501251B1

    公开(公告)日：2002-12-31

    申请号：US09971258

    申请日：2001-10-04

    申请人： Larry Eugene Mosley ,  Edward R. Stanford

    发明人： Larry Eugene Mosley ,  Edward R. Stanford

    IPC分类号： G05F159

    CPC分类号： G06F1/26

    摘要： A system includes a junction-field-effect transistor and a transmission line. The transmission line is coupled to the transistor to communicate a supply voltage from a first end of the transmission line to a first circuit located near a second end of the transmission line. The system also includes a second circuit to control operation of the transistor to regulate a decrease in the supply voltage between the first end of the transmission and the first circuit.

    摘要翻译： 一种系统包括结场效应晶体管和传输线。 传输线耦合到晶体管，以将来自传输线的第一端的电源电压传送到位于传输线第二端附近的第一电路。 该系统还包括第二电路，用于控制晶体管的操作，以调节传输的第一端和第一电路之间的电源电压的降低。

    Flip-chip on flex for high performance packaging applications
    5.
    发明授权
    Flip-chip on flex for high performance packaging applications 有权
    用于高性能封装应用的Flip-chip for flex

    公开(公告)号：US06365962B1

    公开(公告)日：2002-04-02

    申请号：US09538327

    申请日：2000-03-29

    申请人： Chunlin Liang ,  Larry Eugene Mosley ,  Xiao-Chun Mu

    发明人： Chunlin Liang ,  Larry Eugene Mosley ,  Xiao-Chun Mu

    IPC分类号： H01L23495

    CPC分类号： H01L25/18 ,  H01L23/5387 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19106 ,  H05K1/185 ,  H05K3/4614 ,  H05K3/4623 ,  H01L2924/00 ,  H01L2224/0401

    摘要： According to an embodiment of the invention, an integrated circuit (IC) package is provided that includes a flexible circuit board that has a first surface and a second surface. An integrated circuit mounted to the first surface of the flexible circuit board is provided. An electrical element is attached to the second surface of the flexible circuit board. Also, an encapsulant is attached to the flexible circuit board and the integrated circuit. The flexible circuit board includes at least one layer of dielectric that is no greater than approximately 35 microns thick. In another embodiment, the integrated circuit and the electrical element may be interchanged. A method is provided including attaching an encapsulant to an IC, forming a substrate from at least one layer of dielectric, attaching at least one electrical contact to the substrate, and attaching the substrate to the encapsulant so that the substrate is connected to the IC. Also, an electrical element may be attached with a flip-chip C4 (controlled collapsed chip connection) process.

    摘要翻译： 根据本发明的实施例，提供了一种集成电路（IC）封装，其包括具有第一表面和第二表面的柔性电路板。 提供安装到柔性电路板的第一表面的集成电路。 电元件附接到柔性电路板的第二表面。 此外，密封剂附接到柔性电路板和集成电路。 柔性电路板包括不大于约35微米厚的至少一层电介质。 在另一个实施例中，集成电路和电气元件可以互换。 提供了一种方法，包括将密封剂附着到IC，从至少一层电介质形成衬底，将至少一个电接触附接到衬底，以及将衬底附接到密封剂，使得衬底连接到IC。 此外，电元件可以用倒装芯片C4（受控的塌陷芯片连接）工艺附接。

    High performance capacitor
    7.
    发明授权
    High performance capacitor 有权

    公开(公告)号：US06801422B2

    公开(公告)日：2004-10-05

    申请号：US09473315

    申请日：1999-12-28

    申请人： Larry Eugene Mosley

    发明人： Larry Eugene Mosley

    IPC分类号： H01G4228

    CPC分类号： H01G4/30 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K1/0231 ,  H05K3/3436 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2224/05599

    摘要： A capacitor includes a controlled collapse chip connection system coupled by vias to a plurality of conductive layers embedded in a dielectric. The capacitor and a die can each be mounted on opposite surfaces of a substrate using a controlled collapse chip connection. The controlled collapse chip connection provides a large number of leads for coupling to the conductive layers of the capacitor. The large number of leads reduce the inductance in the connection. For a thin substrate, the length of the conductive material connecting the capacitor to the die is short, and the inductance and resistance of the conductive material is low. A system comprising two dies can be fabricated in a small volume using a plurality of substrates and a single controlled collapse chip connection compatible capacitor for decoupling the two dies.

    High performance capacitor
    8.
    发明授权
    High performance capacitor 失效
    高性能电容器

    公开(公告)号：US06770969B2

    公开(公告)日：2004-08-03

    申请号：US10075659

    申请日：2002-02-13

    申请人： Larry Eugene Mosley

    发明人： Larry Eugene Mosley

    IPC分类号： H01L2362

    CPC分类号： H01G4/30 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K1/0231 ,  H05K3/3436 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2224/05599

    摘要： A capacitor includes a controlled collapse chip connection system coupled by vias to a plurality of conductive layers embedded in a dielectric. The capacitor and a die can each be mounted on opposite surfaces of a substrate using a controlled collapse chip connection. The controlled collapse chip connection provides a large number of leads for coupling to the conductive layers of the capacitor. The large number of leads reduce the inductance in the connection. For a thin substrate, the length of the conductive material connecting the capacitor to the die is short, and the inductance and resistance of the conductive material is low. A system comprising two dies can be fabricated in a small volume using a plurality of substrates and a single controlled collapse chip connection compatible capacitor for decoupling the two dies.

    摘要翻译： 电容器包括通过通孔耦合到嵌入电介质中的多个导电层的受控崩溃芯片连接系统。 使用受控的崩溃芯片连接，电容器和管芯可以分别安装在基板的相对表面上。 受控的崩溃芯片连接提供大量的引线用于耦合到电容器的导电层。 大量的引线减少了连接中的电感。 对于薄的衬底，将电容器连接到管芯的导电材料的长度很短，并且导电材料的电感和电阻低。 可以使用多个基板和单个控制的崩溃芯片连接兼容电容器，以小体积制造包括两个管芯的系统，用于去耦合两个管芯。