利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

113 条记录 (耗时 0.032 秒)

    Electronic Devices, Memory Devices and Memory Arrays
    2.
    发明申请
    Electronic Devices, Memory Devices and Memory Arrays 有权
    电子设备，存储器件和存储器阵列

    公开(公告)号：US20120074373A1

    公开(公告)日：2012-03-29

    申请号：US12893992

    申请日：2010-09-29

    申请人： D.V. Nirmal Ramaswamy ,  Kirk D. Prall

    发明人： D.V. Nirmal Ramaswamy ,  Kirk D. Prall

    IPC分类号： H01L45/00

    CPC分类号： H01L45/14 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

    摘要： Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

    摘要翻译： 一些实施例包括具有串联连接的两个电容器的电子设备。 两个电容器共享一个公共电极。 电容器中的一个包括半导体衬底的区域和这种区域与公共电极之间的电介质。 电容器中的另一个包括在第二电极和公共电极之间的第二电极和离子传导材料。 第一和第二电极中的至少一个具有直接抵靠离子导电材料的电化学活性表面。 一些实施例包括具有串联连接的两个电容器的存储单元，并且一些实施例包括包含这种存储单元的存储器阵列

    NROM memory cell, memory array, related devices and methods
    4.
    发明授权
    NROM memory cell, memory array, related devices and methods 有权

    公开(公告)号：US08441056B2

    公开(公告)日：2013-05-14

    申请号：US12795906

    申请日：2010-06-08

    申请人： Kirk D. Prall ,  Leonard Forbes

    发明人： Kirk D. Prall ,  Leonard Forbes

    IPC分类号： H01L29/72

    CPC分类号： H01L27/11568 ,  G11C11/5692 ,  G11C16/0475 ,  H01L27/115

    摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

    Non-volatile memory cell devices and methods
    7.
    发明授权
    Non-volatile memory cell devices and methods 有权
    非易失性存储单元器件及方法

    公开(公告)号：US08268692B2

    公开(公告)日：2012-09-18

    申请号：US13154618

    申请日：2011-06-07

    申请人： Gurtej S. Sandhu ,  Kirk D. Prall

    发明人： Gurtej S. Sandhu ,  Kirk D. Prall

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

    摘要： A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.

    摘要翻译： 一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。 为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。

    NON-VOLATILE MEMORY CELL DEVICES AND METHODS
    9.
    发明申请
    NON-VOLATILE MEMORY CELL DEVICES AND METHODS 有权
    非易失性存储器单元和方法

    公开(公告)号：US20110233641A1

    公开(公告)日：2011-09-29

    申请号：US13154618

    申请日：2011-06-07

    申请人： Gurtej S. Sandhu ,  Kirk D. Prall

    发明人： Gurtej S. Sandhu ,  Kirk D. Prall

    IPC分类号： H01L29/788 ,  B82Y99/00

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

    摘要： A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.

    摘要翻译： 一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。 为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。

    NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
    10.
    发明申请
    NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS 有权
    NROM存储单元，存储阵列，相关设备和方法

    公开(公告)号：US20100244117A1

    公开(公告)日：2010-09-30

    申请号：US12795906

    申请日：2010-06-08

    申请人： Kirk D. Prall ,  Leonard Forbes

    发明人： Kirk D. Prall ,  Leonard Forbes

    IPC分类号： H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  G11C11/5692 ,  G11C16/0475 ,  H01L27/115

    摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

    摘要翻译： 配置为存储每个F2的至少一个位的存储器单元的阵列包括基本上垂直的结构，提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。 提供电子存储器功能的结构被配置为存储每个门多于一个位。 阵列还包括到存储器单元的电接触，包括基本垂直的结构。 电池可以被编程为具有与栅极绝缘体相邻的多个电荷水平中的一个，其邻近于第一源极/漏极区域，使得沟道区域具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2） 并且使得编程单元以降低的漏极源电流工作。