Method and apparatus for optimizing the display of forms in a data
processing system
    3.
    发明授权
    Method and apparatus for optimizing the display of forms in a data processing system 失效
    用于优化数据处理系统中的表单的显示的方法和装置

    公开(公告)号:US5771371A

    公开(公告)日:1998-06-23

    申请号:US709337

    申请日:1996-09-04

    CPC分类号: G06T11/203 G09G5/24 G09G5/393

    摘要: A method and apparatus for increasing efficiency in displaying characters on a display within the data processing system. A plurality of processes for displaying characters on the display in a data processing system are provided. Each of the processes requires a different amount of processor resources to display characters on the display. One of the processes is selected such that the selected process provides a more efficient display of characters on the display than other processes. Characters may be displayed by caching font data in system memory of the data processing system. Glyph bitmaps for a particular character may be moved from the cache to a graphics adapter utilizing a permanent move instruction available in the CPU. Characters are moved to the graphics adapter on a fixed scanline basis, either encompassing the entire width of the character or the entire string of characters on a line.

    摘要翻译: 一种用于提高在数据处理系统内的显示器上显示字符效率的方法和装置。 提供了用于在数据处理系统中的显示器上显示字符的多个处理。 每个进程需要不同数量的处理器资源来在显示器上显示字符。 选择其中一个过程,使得所选择的过程在显示器上提供比其他处理更有效的显示字符。 可以通过在数据处理系统的系统存储器中缓存字体数据来显示字符。 可以使用CPU中可用的永久移动指令,将特定字符的字形位图从高速缓存移动到图形适配器。 字符以固定的扫描线移动到图形适配器,包括字符的整个宽度或一行中的整个字符串。

    CPU mode-based cache allocation for image data
    4.
    发明授权
    CPU mode-based cache allocation for image data 失效
    基于CPU模式的图像数据缓存分配

    公开(公告)号:US07536511B2

    公开(公告)日:2009-05-19

    申请号:US11482454

    申请日:2006-07-07

    IPC分类号: G06F13/00

    摘要: An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a plurality of cache lines, and memory controller having an input to receive the status indicator. The memory controller is configured to disable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an active mode. The memory controller further is configured to enable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an idle mode.

    摘要翻译: 一种装置包括具有提供状态指示符的输出的中央处理单元,具有可耦合到显示接口的输出的图形控制器,包括多个高速缓存线的高速缓存器以及具有用于接收状态指示器的输入的存储器控​​制器。 存储器控制器被配置为响应于指示中央处理单元处于活动模式的状态指示符,禁止对来自图形控制器的数据请求的高速缓存未命中的高速缓存行的分配。 存储器控制器还被配置为响应于指示中央处理单元处于空闲模式的状态指示符,能够为来自图形控制器的数据请求的高速缓存未命中分配缓存的高速缓存行。

    CPU mode-based cache allocation for image data
    5.
    发明申请
    CPU mode-based cache allocation for image data 失效
    基于CPU模式的图像数据缓存分配

    公开(公告)号:US20080007561A1

    公开(公告)日:2008-01-10

    申请号:US11482454

    申请日:2006-07-07

    IPC分类号: G09G5/36

    摘要: An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a plurality of cache lines, and memory controller having an input to receive the status indicator. The memory controller is configured to disable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an active mode. The memory controller further is configured to enable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an idle mode.

    摘要翻译: 一种装置包括具有提供状态指示符的输出的中央处理单元,具有可耦合到显示接口的输出的图形控制器,包括多个高速缓存线的高速缓存器以及具有用于接收状态指示器的输入的存储器控​​制器。 存储器控制器被配置为响应于指示中央处理单元处于活动模式的状态指示符,禁止对来自图形控制器的数据请求的高速缓存未命中的高速缓存行的分配。 存储器控制器还被配置为响应于指示中央处理单元处于空闲模式的状态指示符,能够为来自图形控制器的数据请求的高速缓存未命中分配缓存的高速缓存行。