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公开(公告)号：US07890706B2
公开(公告)日：2011-02-15
申请号：US10990151
申请日：2004-11-16
IPC分类号： G06F13/14
CPC分类号： G06F11/1658 , G06F9/52 , G06F11/1641 , G06F11/1645 , G06F11/165 , G06F11/1683 , G06F11/1687 , G06F11/184 , G06F11/185 , G06F11/3404 , G06F11/3476 , G06F11/3495 , G06F11/3636 , G06F11/366 , G06F2201/88
摘要： In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors.
摘要翻译： 在包括多片处理器和存储器的系统中，具有竞争回避能力的同步单元包括委托写入引擎，其从处理器接收数据和存储器地址信息，并将数据作为处理器的代理将数据写入存储器。
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2.发明授权Method and apparatus to allow dynamic variation of ordering enforcement between transactions in a strongly ordered computer interconnect 有权允许在强有序的计算机互连中的事务之间的排序执行的动态变化的方法和装置公开(公告)号：US07308522B2
公开(公告)日：2007-12-11
申请号：US10864617
申请日：2004-06-09
IPC分类号： G06F13/36
CPC分类号： G06F13/423 , G06F13/364 , G06F13/4059
摘要： A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.
摘要翻译： 对连接到强有序总线的适配器单元执行读写事务的排序的方法。 适配器单元具有一组读缓冲器和写缓冲器。 启动器写入事务和目标读取完成事务按照接收事务的原始顺序在总线上执行。 启动器读取事务请求在读取缓冲器中排队，但是在将读取事务请求呈现给总线之前，有选择地等待写入缓冲区中的一个或多个待处理的发起者写入事务的执行。 以这种方式，在执行启动器读取事务请求之前，读取事务请求在写缓冲区中依赖和挂起的发起者写入事务在发起者读取事务请求之前被退回到总线，从而确保发起者读取事务请求在启动器写入之前不被执行 读取事务请求所依赖的事务。
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3.发明授权Method and apparatus to allow dynamic variation of ordering enforcement between transactions in a strongly ordered computer interconnect 失效允许在强有序的计算机互连中的事务之间的排序执行的动态变化的方法和装置公开(公告)号：US06754737B2
公开(公告)日：2004-06-22
申请号：US10035983
申请日：2001-12-24
IPC分类号： G06F300
CPC分类号： G06F13/423 , G06F13/364 , G06F13/4059
摘要： A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.
摘要翻译： 对连接到强有序总线的适配器单元执行读写事务的排序的方法。 适配器单元具有一组读缓冲器和写缓冲器。 启动器写入事务和目标读取完成事务按照接收事务的原始顺序在总线上执行。 启动器读取事务请求在读取缓冲器中排队，但是在将读取事务请求呈现给总线之前，有选择地等待写入缓冲区中的一个或多个待处理的发起者写入事务的执行。 以这种方式，在执行启动器读取事务请求之前，读取事务请求在写缓冲区中依赖和挂起的发起者写入事务在发起者读取事务请求之前被退回到总线，从而确保发起者读取事务请求在启动器写入之前不被执行 读取事务请求所依赖的事务。
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公开(公告)号：US08799706B2
公开(公告)日：2014-08-05
申请号：US11042985
申请日：2005-01-25
申请人： William F. Bruckert , David J. Garcia , Thomas A. Heynemann , James S. Klecka , Jeffrey A. Sprouse
发明人： William F. Bruckert , David J. Garcia , Thomas A. Heynemann , James S. Klecka , Jeffrey A. Sprouse
IPC分类号： G06F11/00
CPC分类号： G06F11/1687 , G06F11/1645
摘要： A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.
摘要翻译： 一种在处理器之间交换信息的方法和系统。 说明性实施例中的至少一些可以是一种方法，包括通过将（第一处理器）第一数据写入逻辑设备，然后由第一处理器继续处理用户程序，在多个处理器之间交换信息，由（第 第二处理器）到逻辑设备的第二数据，然后由第二处理器继续处理用户程序，并且在所有处理器具有第一处理器和第二处理器之后，通过逻辑器件将第一和第二数据写入第一和第二处理器 将其各自的基准写入逻辑设备。
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5.发明授权System and method for performing improved pseudo-random testing of systems having multi driver buses 失效用于执行具有多个驱动器总线的系统的改进的伪随机测试的系统和方法
公开(公告)号：US5951703A
公开(公告)日：1999-09-14
申请号：US083419
申请日：1993-06-28
IPC分类号： G06F11/22 , G01R31/3185 , G06F11/267 , G06F11/27 , G06F13/00 , G06F13/36 , G01R31/28
CPC分类号： G06F11/2221 , G01R31/318385 , G01R31/318555 , G06F11/27
摘要： A digital system includes a number of digital subsystems interconnected by a shared bus structure that is mutually exclusively accessible for communicating data between the subsystems. The system is structured to be tested by pseudo-random scan test methodology. Each subsystem includes a counter that, during scan test periods, provides an enable signal to the bus access or driver circuitry of the associated subsystem. A scan test operation is preceded by pre-loading each counter with a predetermined state so that, initially, and throughout the test period, one and only one digital subsystem will drive the shared data bus. Each scan sequence (comprising a scan in, an execution cycle, and a scan out of the pseudo-random test strings) will result in the counters being clocked once so that a new subsystem will be enable to drive the bus the next sequence, permitting the bus access circuitry of each subsystem, and the bus itself, to be tested.
摘要翻译： 数字系统包括通过共享总线结构互连的多个数字子系统，该共享总线结构相互独占可访问以在子系统之间传送数据。 该系统的结构是通过伪随机扫描测试方法进行测试。 每个子系统包括一个计数器，在扫描测试期间，向相关子系统的总线访问或驱动器电路提供使能信号。 在扫描测试操作之前，以预定状态预加载每个计数器，使得最初和整个测试周期中，只有一个数字子系统将驱动共享数据总线。 每个扫描序列（包括扫描，执行周期和伪随机测试字符串中的扫描）将导致计数器被计时一次，以便新的子系统将能够驱动总线下一个序列，从而允许 每个子系统的总线访问电路和总线本身进行测试。
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