-
公开(公告)号：US06732242B2
公开(公告)日：2004-05-04
申请号：US10113546
申请日：2002-03-28
IPC分类号： G06F1300
CPC分类号： G06F13/161 , G06F9/383 , G06F12/0862
摘要： A transaction management system is described for scheduling requests on an external bus. The system includes a number of queue registers to store requests and a controller coupled to queue registers to schedule external bus transactions for an agent that processes read requests, prefetch requests and write requests. The controller posts at least one write request to an external bus every defined number of transactions if at least one non-posted write request is stored in the queue registers.
摘要翻译： 描述了用于在外部总线上调度请求的事务管理系统。 该系统包括多个用于存储请求的队列寄存器和耦合到队列寄存器的控制器，为处理读取请求，预取请求和写入请求的代理程序调度外部总线事务。 如果至少一个非发布的写入请求存储在队列寄存器中，控制器将每个定义数量的事务发送至少一个写入请求给外部总线。
-
公开(公告)号：US06578114B2
公开(公告)日：2003-06-10
申请号：US10180009
申请日：2002-06-26
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.
-
公开(公告)号：US06434677B1
公开(公告)日：2002-08-13
申请号：US09323360
申请日：1999-06-01
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.
-
4.发明授权Method and apparatus for altering data length to zero to maintain cache coherency 失效将数据长度改变为零以维持高速缓存一致性的方法和装置公开(公告)号：US06735675B2
公开(公告)日：2004-05-11
申请号：US10346060
申请日：2003-01-17
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.
摘要翻译： 通过允许所有显式回写在窥探阶段继续进行，从而提高了多代理系统的效率。 在每个传入的外部总线请求时，代理确定该请求的地址是否匹配代理中的数据的地址。 如果有匹配，代理将复制最近的数据，将数据的状态更改为未修改，将数据的长度更改为零（用于挂起的显式回写），并执行隐式的回写。 另外，在每个显式回写之前，代理确定显式回写的地址和任何进入的窥探请求请求是否相同。 如果存在匹配，代理将在显式回写之前将显式回写的数据长度更改为零。
-
公开(公告)号：US07487305B2
公开(公告)日：2009-02-03
申请号：US11557183
申请日：2006-11-07
申请人： David L. Hill , Derek T. Bachand
发明人： David L. Hill , Derek T. Bachand
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F12/0862 , G06F13/18 , G06F13/362
摘要： A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
-
公开(公告)号：US06269465B1
公开(公告)日：2001-07-31
申请号：US09197582
申请日：1998-11-23
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
IPC分类号： H03M1300
CPC分类号： H03M13/03
摘要： An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.
摘要翻译： 代理中的纠错系统在从内部高速缓存延伸到代理的输出的电路中提供纠错。 当检测到在代理内部要处理的数据的数据错误时，纠错系统将损坏的数据通过纠错电路，并从代理程序中传回代理。 当检测到数据错误时，错误修正将内部数据请求更改为外部事务。
-
公开(公告)号：US07143242B2
公开(公告)日：2006-11-28
申请号：US10667457
申请日：2003-09-23
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F13/18 , G06F13/362
摘要： A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.
-
公开(公告)号：US06782457B2
公开(公告)日：2004-08-24
申请号：US10454625
申请日：2003-06-05
申请人： David L Hill , Derek T. Bachand
发明人： David L Hill , Derek T. Bachand
IPC分类号： G06F1300
CPC分类号： G06F13/1642 , G06F12/0862 , G06F13/18 , G06F13/362
摘要： A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
摘要翻译： 调度器存储要调度的数据。 调度器可以包括根据第一优先级方案（例如按年龄）标识队列条目中的相对优先级的阵列。 调度器还可以包括优先级寄存器阵列，其根据第二优先级方案，例如通过数据类型来标识队列条目中的相对优先级。 耦合到阵列和优先级寄存器阵列的多个检测器可以确定下一个要调度的数据。
-
公开(公告)号：US06216208B1
公开(公告)日：2001-04-10
申请号：US08999241
申请日：1997-12-29
IPC分类号： G05F1208
CPC分类号： G06F9/383 , G06F12/0862 , G06F2212/6026
摘要： A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.
摘要翻译： 为处理器提供的预取控制系统。 预取队列可以包括仲裁器，高速缓存队列和预取队列。 仲裁器发出请求，包括读取请求。 响应于读取请求，缓存队列发出控制信号。 预取队列接收控制信号和与读取请求相关联的地址。 当接收到的地址是来自顺序存储器位置的读取请求的模式的成员时，预取队列向仲裁器发出预取请求。
-
公开(公告)号：US06209068B1
公开(公告)日：2001-03-27
申请号：US08999242
申请日：1997-12-29
IPC分类号： G06F1216
CPC分类号： G06F12/0831
摘要： A data control method in a microprocessor is disclosed. According to the method, a request is generated on an external bus for data to be read to the processor. The requested data is read from the external bus to an intermediate memory in the processor and, thereafter, read from the intermediate memory to a destination. When the intermediate memory is full, the read of data from the external bus is stalled until the intermediate memory is no longer full. Typically, stalling is accomplished by generating a stall signal on the external bus, which may be generated during a cache coherency phase of the transaction to which the requested data relates.
摘要翻译： 公开了一种微处理器中的数据控制方法。 根据该方法，在外部总线上生成要向处理器读取的数据的请求。 所请求的数据从外部总线读取到处理器中的中间存储器，然后从中间存储器读取到目的地。 当中间存储器满时，来自外部总线的数据读取停止，直至中间存储器不再满。 通常，停止是通过在外部总线上生成停止信号来实现的，该停止信号可以在所请求的数据所关联的事务的高速缓存一致性阶段期间产生。
-
-
-
-
-
-
-
-
-
搜索结果
24 条记录 (耗时 0.023 秒)
