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公开(公告)号：US06732242B2
公开(公告)日：2004-05-04
申请号：US10113546
申请日：2002-03-28
IPC分类号： G06F1300
CPC分类号： G06F13/161 , G06F9/383 , G06F12/0862
摘要： A transaction management system is described for scheduling requests on an external bus. The system includes a number of queue registers to store requests and a controller coupled to queue registers to schedule external bus transactions for an agent that processes read requests, prefetch requests and write requests. The controller posts at least one write request to an external bus every defined number of transactions if at least one non-posted write request is stored in the queue registers.
摘要翻译： 描述了用于在外部总线上调度请求的事务管理系统。 该系统包括多个用于存储请求的队列寄存器和耦合到队列寄存器的控制器，为处理读取请求，预取请求和写入请求的代理程序调度外部总线事务。 如果至少一个非发布的写入请求存储在队列寄存器中，控制器将每个定义数量的事务发送至少一个写入请求给外部总线。
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公开(公告)号：US08205111B2
公开(公告)日：2012-06-19
申请号：US12348054
申请日：2009-01-02
申请人： David L. Hill , Robert J. Greiner , Tim Frodsham , Derek Bachand , Anant Deval , Mark Waggoner
发明人： David L. Hill , Robert J. Greiner , Tim Frodsham , Derek Bachand , Anant Deval , Mark Waggoner
CPC分类号： G06F1/10
摘要： In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种根据写入器的第一时钟将来自耦合到读取器的写入器的数据经由管芯内互连写入队列条目的方法，生成读取器的哪个第二时钟的映射 允许读取器至少部分地基于第一和第二时钟从队列中读取，并且在允许的第二时钟从条目读取数据。 描述和要求保护其他实施例。
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公开(公告)号：US06907487B2
公开(公告)日：2005-06-14
申请号：US09783852
申请日：2001-02-14
CPC分类号： G06F13/4217
摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.
摘要翻译： 可用于增强的高流水线总线架构中的总线代理。 在一个实施例中，总线代理包括用于以时钟频率驱动控制信号的控制接口，用于以两倍时钟频率驱动地址元件的地址总线接口和用于以四倍于时钟频率驱动数据元素的数据总线接口 。 地址总线接口为每个地址元件驱动基本中心的地址选通转换，并且数据总线接口为每个数据元件驱动基本中心的数据选通转换。
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公开(公告)号：US20100174936A1
公开(公告)日：2010-07-08
申请号：US12348054
申请日：2009-01-02
申请人： David L. Hill , Robert J. Greiner , Tim Frodsham , Derek Bachand , Anant Deval , Mark Waggoner
发明人： David L. Hill , Robert J. Greiner , Tim Frodsham , Derek Bachand , Anant Deval , Mark Waggoner
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种根据写入器的第一时钟将来自耦合到读取器的写入器的数据经由管芯内互连写入队列条目的方法，生成读取器的哪个第二时钟的映射 允许读取器至少部分地基于第一和第二时钟从队列中读取，并且在允许的第二时钟从条目读取数据。 描述和要求保护其他实施例。
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公开(公告)号：US06807592B2
公开(公告)日：2004-10-19
申请号：US09925691
申请日：2001-08-10
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.
摘要翻译： 双向多点处理器总线连接到多个总线代理。 可以通过以多抽头信令模式操作总线来增加总线吞吐量，其中多个信息元素以驱动代理以总线时钟频率的倍数的速率被驱动到总线上。 驱动代理还激活选通以识别信息元素的采样点。 可以例如使用双泵浦信号模式来驱动请求的信息元素，其中在一个总线时钟周期期间驱动两个信息元素。 数据线传输的数据元素例如可以使用四泵浦信号模式来驱动，其中四个数据元件在一个总线时钟周期内被驱动。 可以以偏移或交错布置临时地激活多个选通信号，以减少选通信号的频率。 可以通过仅使用选通信号的一种类型的边缘（例如，上升沿或下降沿）来提高采样对称性，以识别采样点。
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公开(公告)号：US06804735B2
公开(公告)日：2004-10-12
申请号：US09784244
申请日：2001-02-14
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.
摘要翻译： 可用于增强的高流水线总线架构中的总线代理。 在一个实施例中，总线代理包括目标就绪接口，用于一组响应信号的一组响应接口和数据总线忙接口以及用于总线时钟信号的总线时钟接口。 该实施例的总线代理还包括总线控制器逻辑以跟踪包括事务N-1和事务N的多个事务，总线控制器能够为事务N断言目标就绪信号，如果总线代理正在断言数据 忙信号用于事务N-1，并取消对数据忙信号的否定。
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公开(公告)号：US07783809B2
公开(公告)日：2010-08-24
申请号：US11173643
申请日：2005-06-30
申请人： Keshavan K. Tiruvallur , David I. Poisner , Herbert H. J. Hum , Frank Binns , David L. Hill , Robert J. Greiner , Raymond S. Tetrick
发明人： Keshavan K. Tiruvallur , David I. Poisner , Herbert H. J. Hum , Frank Binns , David L. Hill , Robert J. Greiner , Raymond S. Tetrick
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.
摘要翻译： 允许传统引脚功能被替换为“虚拟线”的架构和技术，“虚拟线”可以传达否则将由有线接口传送的信息。 可以在系统控制器和包括虚拟线路值和虚拟换线指示器的处理器之间传递消息。 虚拟线值可以包括对应于已经从物理接口消除的一个或多个引脚的信号，并且虚拟线更改值可以包括虚拟线值是否已经改变的指示。 虚拟线路值和虚拟线路变化指示器的组合可以允许多个物理引脚被消息值替换。
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公开(公告)号：US06880031B2
公开(公告)日：2005-04-12
申请号：US09783784
申请日：2001-02-14
CPC分类号： G06F13/4217
摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic capable of sensing or asserting one or more of a set of snoop status signals for transaction N on the snoop status interfaces during a snoop phase to start in a bus cycle upon the later of three or more bus clock cycles of the bus clock signal after a beginning of a bus cycle of an the assertion of an address strobe signal for transaction N or two or more bus clock cycles of the bus clock signal after a beginning of a bus cycle in which a most recent snoop phase begins.
摘要翻译： 可用于增强的高流水线总线架构中的总线代理。 在一个实施例中，总线代理包括一组窥探状态接口，地址选通信号接口和用于总线时钟信号的总线时钟接口。 该实施例的总线代理还包括总线控制器逻辑，其能够在探测阶段期间在监听阶段中在三个或更多的后期的总线周期中检测或断言用于事件N的一组窥探状态信号中的一个或多个窥探状态信号 总线时钟信号的总线时钟周期在总线周期开始之后，在总线周期开始之后断言事务N的地址选通信号或总线时钟信号的两个或多个总线时钟周期，其中a 最近的窥探阶段开始了。
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公开(公告)号：US06609171B1
公开(公告)日：2003-08-19
申请号：US09474058
申请日：1999-12-29
IPC分类号： G06F112
CPC分类号： G06F13/4217
摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.
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公开(公告)号：US06601121B2
公开(公告)日：2003-07-29
申请号：US09925692
申请日：2001-08-10
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.
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