Circuit utilizing resistors trimmed by metal migration
    1.
    发明授权
    Circuit utilizing resistors trimmed by metal migration 失效
    利用金属迁移修剪电路的电路

    公开(公告)号:US4725791A

    公开(公告)日:1988-02-16

    申请号:US908858

    申请日:1986-09-18

    CPC classification number: H01L27/0802 H01L23/647 H03F3/45479 H01L2924/0002

    Abstract: An operational amplifier of the type which includes first and second differentially coupled input transistors which cooperate with a current mirror circuit also includes a first and second RTMM resistors which may be individually trimmed to reduce input offset voltage. Each RTMM resistor is coupled from the power supply rail through first and second diodes respectively to the first and second input terminals. In this manner, signals appearing on the input terminals which exceed the rail voltage will cause currents to flow through the RTMM resistors thus reducing their resistance, and reducing offset voltage.

    Abstract translation: 包括与电流镜电路配合的第一和第二差分耦合输入晶体管的类型的运算放大器还包括第一和第二RTMM电阻器,其可被单独修整以减少输入偏移电压。 每个RTMM电阻器通过第一和第二二极管分别从电源轨耦合到第一和第二输入端。 以这种方式,输入端子出现的超过轨电压的信号将导致电流流过RTMM电阻器,从而降低其电阻,并降低失调电压。

    Circuit and method of modifying characteristics of a utilization circuit
    3.
    发明授权
    Circuit and method of modifying characteristics of a utilization circuit 失效
    修改利用电路特性的电路及方法

    公开(公告)号:US5679275A

    公开(公告)日:1997-10-21

    申请号:US497760

    申请日:1995-07-03

    CPC classification number: H01C17/267

    Abstract: A modification circuit (30) is thermally coupled to and electrically isolated from a circuit element (20) of a utilization circuit (10). During modification, current pulses are passed through an isolation circuit (40) to the modification circuit which heats the circuit element, e.g., a resistor, of the utilization circuit substantially above the normal operating temperature range of the element, thereby modifying the electrical characteristics of the resistor and therefore those of the utilization circuit to which it is connected. During normal operation of the utilization circuit the circuit element of the utilization circuit is electrically isolated from the modification circuit.

    Abstract translation: 修改电路(30)热耦合到利用电路(10)的电路元件(20)并与其电隔离。 在修改期间,电流脉冲通过隔离电路(40)到修改电路,该修改电路将利用电路的电路元件(例如,电阻器)加热到基本上高于元件的正常工作温度范围,从而改变元件的电特性 电阻器,因此与其连接的利用电路的电阻器。 在利用电路的正常操作期间,利用电路的电路元件与修改电路电隔离。

    Operational amplifier utilizing resistors trimmed by metal migration
    4.
    发明授权
    Operational amplifier utilizing resistors trimmed by metal migration 失效
    使用通过金属迁移修剪的电阻的运算放大器

    公开(公告)号:US4717886A

    公开(公告)日:1988-01-05

    申请号:US880537

    申请日:1986-06-30

    Abstract: First and second resistors of a resistive network formed in a semiconductive substrate may be individually trimmed. The first and second resistive regions coupled at one end thereof have their other ends provided with metallic contacts. The resistive regions are disposed on the substrate such that current flowing from the first metallic contact to the second metallic contact through the first and second resistive regions causes the resistance of the first resistive region to be preferentially reduced. In contrast, current flowing from the second metallic contact to the first metallic contact through the first and second resistive regions causes the resistance of the second resistive region to be preferentially reduced. The resistive network is used in an operational amplifier circuit so as to permit the input offset voltage to be substantially reduced by selective trimming.

    Abstract translation: 形成在半导体衬底中的电阻网络的第一和第二电阻器可以被单独修整。 在其一端耦合的第一和第二电阻区域的另一端设有金属触点。 电阻区域设置在基板上,使得从第一金属接触件流到第二金属接触件的电流通过第一和第二电阻区域导致第一电阻区域的电阻被优先减小。 相反,通过第一和第二电阻区域从第二金属触点流向第一金属触点的电流导致第二电阻区域的电阻被优先减小。 电阻网络用于运算放大器电路中,以便通过选择性修整来大大减少输入失调电压。

    Operational amplifier utilizing FET followers and feed-forward capacitors
    5.
    发明授权
    Operational amplifier utilizing FET followers and feed-forward capacitors 失效
    使用FET跟随器和前馈电容器的运算放大器

    公开(公告)号:US4717885A

    公开(公告)日:1988-01-05

    申请号:US909808

    申请日:1986-09-22

    CPC classification number: H03F1/086 H03F3/505

    Abstract: An improved field effect transistor follower circuit includes a transistor having equivalent input capacitance C.sub..pi. and a field-effect-transistor which has a gate electrode coupled to a source of an input signal, a drain coupled to a source of supply voltage, and a source coupled to the base of the transistor. A feed forward capacitor is provided and coupled between the gate and source electrodes of the field effect transistor. An operational amplifier is also disclosed which utilizes junction field-effect-transistor followers including feed forward capacitors.

    Abstract translation: 改进的场效应晶体管跟随器电路包括具有等效输入电容C pi的晶体管和场效应晶体管,场效应晶体管具有耦合到输入信号源的栅极电极,耦合到电源电压源的漏极和源极 耦合到晶体管的基极。 提供前馈电容器并耦合在场效应晶体管的栅极和源极之间。 还公开了一种运算放大器,其利用包括前馈电容器的结型场效应晶体管跟随器。

    Output stage for an operational amplifier
    6.
    发明授权
    Output stage for an operational amplifier 失效
    运算放大器的输出级

    公开(公告)号:US4922208A

    公开(公告)日:1990-05-01

    申请号:US334430

    申请日:1989-04-07

    CPC classification number: H03F1/0261 H03F3/3096

    Abstract: In an output stage of an operational amplifier comprising first and second NPN output transistors a circuit is coupled between the positive supply conductor and the collector of the first NPN transistor for providing a boosted base current drive thereto as a function of the load current sourced from the emitter of the first transistor to the output of the operational amplifier. The circuit senses the collector current flowing through the first transistor for increasing the base current drive thereto as the collector current increases.

    JFET pinch off voltage proportional reference current generating circuit
    7.
    发明授权
    JFET pinch off voltage proportional reference current generating circuit 失效
    JFET闭合电压比例参考电流发生电路

    公开(公告)号:US4716356A

    公开(公告)日:1987-12-29

    申请号:US943341

    申请日:1986-12-19

    CPC classification number: G05F3/245

    Abstract: A circuit for generating a reference current proportional over temperature to the pinch-off voltage of a first JFET includes second and third JFETS and first and second resistors. The second JFET has its gate coupled to its source and produces a current which drives the first JFET. Since the width-to-length ratio of the second JFET is greater than that of the first, a negative gate-to-source voltage of the first JFET is produced across the first resistor. The third JFET has a source coupled via the second resistor to the gate of the first JFET and has a gate coupled to the drain of the first JFET for setting the voltage thereat. The reference current appears at the drain of the third JFET.

    Abstract translation: 用于产生与第一JFET的夹断电压成比例的参考电流的电路包括第二和第三JFET以及第一和第二电阻器。 第二个JFET的栅极耦合到其源极,并产生驱动第一个JFET的电流。 由于第二JFET的宽度与长度之比大于第一JFET的宽度比,所以第一JFET的负栅极至源极电压跨越第一电阻器产生。 第三JFET具有经由第二电阻器耦合到第一JFET的栅极的源极,并且具有耦合到第一JFET的漏极的栅极,用于在其上设置电压。 参考电流出现在第三JFET的漏极处。

    Circuit and method of biasing a drive transistor to a data bus
    8.
    发明授权
    Circuit and method of biasing a drive transistor to a data bus 失效
    将驱动晶体管偏置到数据总线的电路和方法

    公开(公告)号:US5548233A

    公开(公告)日:1996-08-20

    申请号:US395338

    申请日:1995-02-28

    Applicant: David M. Susak

    Inventor: David M. Susak

    CPC classification number: H03K19/00353

    Abstract: A data transmitter (12) on a data bus (16) keeps its drive transistor (36) at a minimum bias according to the minimum voltage level on the data bus. The current flowing through the drive transistor in response to a data signal, or a proportional current, is mirrored (52, 54) and compared to a current source (60). Any mismatched between the mirrored current and the current source enables a transistor (58) to bias the drive transistor so that it maintains a minimum conduction state. The base of the drive transistor is held one V.sub.be above the minimum voltage on the data bus. The minimum bias on the base of the drive transistor keeps it conducting so that the transition to full conduction is smooth and prevents any sharp transitions that may cause undesired radiated emissions.

    Abstract translation: 数据总线(16)上的数据发送器(12)根据数据总线上的最小电压电平使其驱动晶体管(36)保持最小偏置。 响应于数据信号或比例电流流过驱动晶体管的电流被镜像(52,54)并与电流源(60)进行比较。 在镜像电流和电流源之间的任何不匹配使得晶体管(58)能够偏置驱动晶体管,使得其保持最小导通状态。 驱动晶体管的基极在数据总线上的最小电压以上保持一个Vbe。 驱动晶体管基极的最小偏压保持导通,使得向全导通的转换是平滑的,并且可以防止可能导致不期望的辐射发射的任何尖锐的转变。

    Circuit and method of reverse voltage protection using a lateral
transistor having a collector ring surrounding its base region
    9.
    发明授权
    Circuit and method of reverse voltage protection using a lateral transistor having a collector ring surrounding its base region 失效
    使用具有围绕其基极区域的集电环的横向晶体管的反向电压保护的电路和方法

    公开(公告)号:US5604373A

    公开(公告)日:1997-02-18

    申请号:US415889

    申请日:1995-04-03

    CPC classification number: H01L27/0248

    Abstract: A lateral transistor (14) is configured as a reverse protection diode that allows low and high current modes of operation while maintaining low forward voltage drop. The base region (38) of the lateral transistor is formed inside a collector ring (34) and adjacent to the emitter region (36). In low current mode, the transistor operates as a conventional diode. In high current mode, the excessive number of minority carriers injected into the base region causes the device to enter conductivity modulation that effectively increases the doping concentration and lowers the bulk resistance. The lower bulk resistance keeps the forward voltage drop low. By having the base region inside the collector ring, the bulk resistance is kept low to aid in the onset of conductivity modulation. Thus, the transition between low current mode and high current mode is minimized.

    Abstract translation: 横向晶体管(14)被配置为反向保护二极管,其允许低和高电流工作模式,同时保持低的正向压降。 横向晶体管的基极区域(38)形成在集电环(34)内并与发射极区域(36)相邻。 在低电流模式下,晶体管作为常规二极管工作。 在高电流模式下,注入基区的少数载流子数量过多会导致器件进入电导率调制,从而有效地增加掺杂浓度并降低体电阻。 较低的体积电阻使正向压降保持不变。 通过使基极区域位于集电环内,体电阻保持较低,有助于电导率调制的开始。 因此,低电流模式和高电流模式之间的转换被最小化。

    Circuit and method of measuring squib resistance
    10.
    发明授权
    Circuit and method of measuring squib resistance 失效
    电路和测量爆管阻力的方法

    公开(公告)号:US5506509A

    公开(公告)日:1996-04-09

    申请号:US348631

    申请日:1994-12-05

    Applicant: David M. Susak

    Inventor: David M. Susak

    CPC classification number: B60R21/0173 G01R31/2829 G01R27/14 G01R31/006

    Abstract: A resistance measuring circuit (10) generates a predetermined reference voltage and impresses that reference voltage across a squib detonation device (12). The resulting current flowing through the squib is mirrored by a current mirror (42,52,54) for providing multiple mirrored currents. The mirrored currents are compared to known current sources (58,60). The output signals go high or low depending on whether the mirrored currents are greater than or less than the fixed current sources. The output signals provide an indication as to whether the measured squib resistance is within a specified resistance range. The current sources may be precisely matched to maintain high accuracy in measuring the resistance.

    Abstract translation: 电阻测量电路(10)产生预定的参考电压并且将该参考电压印在跨越爆管装置(12)上。 流过爆管的所得电流由用于提供多个镜像电流的电流镜(42,52,54)反射。 将镜像电流与已知电流源进行比较(58,60)。 取决于镜像电流是否大于或小于固定电流源,输出信号变为高电平或低电平。 输出信号提供关于测量的爆管阻力是否在规定电阻范围内的指示。 电流源可以精确匹配,以在测量电阻时保持高精度。

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