公开(公告)号：US20080310808A1

公开(公告)日：2008-12-18

申请号：US11764447

申请日：2007-06-18

申请人： David Michael Fried ,  Philip Charles Danby Hobbs ,  Nancy Carolyn LaBianca ,  Frank Robert Libsch

发明人： David Michael Fried ,  Philip Charles Danby Hobbs ,  Nancy Carolyn LaBianca ,  Frank Robert Libsch

IPC分类号： G02B6/10 ,  C23F1/02

CPC分类号： G02B6/136

摘要： A photonic waveguide structure includes a first photonic waveguide layer located over a substrate. A sidewall cladding layer is located cladding a sidewall, but not covering a top, of the first photonic waveguide layer. A second photonic waveguide layer may be located upon the top of the sidewall cladding layer while contacting, but not straddling, the first photonic waveguide layer. The sidewall cladding layer protects the first photonic waveguide layer from environmental exposure, thus providing enhanced performance of a photonic waveguide structure. A planarizing sidewall cladding layer allows the fabrication of optical chips with multiple layers of lithographically defined devices.

摘要翻译： 光子波导结构包括位于衬底上的第一光子波导层。 侧壁包层定位为包覆第一光子波导层的侧壁但不覆盖顶部。 第二光子波导层可以位于侧壁包层的顶部，同时接触但不跨越第一光子波导层。 侧壁包覆层保护第一光子波导层免受环境暴露，从而提供光子波导结构的增强的性能。 平面化的侧壁包层允许制造具有多层光刻定义的器件的光学芯片。

公开(公告)号：US08039888B2

公开(公告)日：2011-10-18

申请号：US11848597

申请日：2007-08-31

申请人： Gary Bela Bronner ,  David Michael Fried ,  Jeffrey Peter Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Y. Sardesai

发明人： Gary Bela Bronner ,  David Michael Fried ,  Jeffrey Peter Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Y. Sardesai

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.

摘要翻译： 一种在半导体器件上形成导电间隔物的方法。 该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层 。 任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

公开(公告)号：US20090212388A1

公开(公告)日：2009-08-27

申请号：US12436189

申请日：2009-05-06

申请人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

发明人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

IPC分类号： H01L29/06

CPC分类号： G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.

摘要翻译： 用于将集成电路芯片的制造级别的第一组特征对准到电子束对准目标的结构。 所述结构包括半导体衬底中的第一沟槽，所述第一沟槽从所述衬底的顶表面延伸到所述衬底中第一距离; 在第一沟槽的底部的电子背散射层; 背面散射层上的沟槽中的介电覆盖层; 以及所述衬底中的第二沟槽，所述第二沟槽从所述衬底的顶表面延伸到所述衬底中第二距离，所述第二距离小于所述第一距离。

公开(公告)号：US08120138B2

公开(公告)日：2012-02-21

申请号：US12436189

申请日：2009-05-06

申请人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

发明人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

IPC分类号： H01L23/544

CPC分类号： G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.

摘要翻译： 用于将集成电路芯片的制造级别的第一组特征对准到电子束对准目标的结构。 所述结构包括半导体衬底中的第一沟槽，所述第一沟槽从所述衬底的顶表面延伸到所述衬底中第一距离; 在第一沟槽的底部的电子背散射层; 背面散射层上的沟槽中的介电覆盖层; 以及所述衬底中的第二沟槽，所述第二沟槽从所述衬底的顶表面延伸到所述衬底中第二距离，所述第二距离小于所述第一距离。

公开(公告)号：US07550361B2

公开(公告)日：2009-06-23

申请号：US11618957

申请日：2007-01-02

申请人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

发明人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

IPC分类号： H01L21/76

CPC分类号： H01L21/76283 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01J37/3174 ,  H01L21/3081 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

摘要翻译： 一种用于将集成电路芯片的制造级别的第一组特征对准到形成在衬底中的电子束对准目标并使用电子束光刻形成第一组特征并用于对准第二组特征的方法 将集成电路芯片的制造水平设置到形成在基板中的光学对准目标，并且使用光刻法形成第二组特征，所述光学对准目标本身与电子束对准目标对准。 还有一种形成电子束对准靶的方法和结构。

公开(公告)号：US20080272398A1

公开(公告)日：2008-11-06

申请号：US11848597

申请日：2007-08-31

申请人： Gary Bela Bronner ,  David Michael Fried ,  Jeffrey Peter Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Y. Sardesai

发明人： Gary Bela Bronner ,  David Michael Fried ,  Jeffrey Peter Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Y. Sardesai

IPC分类号： H01L29/00

CPC分类号： H01L21/26586 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.

摘要翻译： 一种在半导体器件上形成导电间隔物的方法。 该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层 。 任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

公开(公告)号：US20080157404A1

公开(公告)日：2008-07-03

申请号：US11618957

申请日：2007-01-02

申请人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

发明人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

IPC分类号： H01L23/544 ,  G03F7/20 ,  H01L21/76

CPC分类号： H01L21/76283 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01J37/3174 ,  H01L21/3081 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

摘要翻译： 一种用于将集成电路芯片的制造级别的第一组特征对准到形成在衬底中的电子束对准目标并使用电子束光刻形成第一组特征并用于对准第二组特征的方法 将集成电路芯片的制造水平设置到形成在基板中的光学对准目标，并且使用光刻法形成第二组特征，所述光学对准目标本身与电子束对准目标对准。 还有一种形成电子束对准靶的方法和结构。

公开(公告)号：US07696057B2

公开(公告)日：2010-04-13

申请号：US11618974

申请日：2007-01-02

申请人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

发明人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

IPC分类号： H01L21/76

CPC分类号： G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

摘要翻译： 一种用于将集成电路芯片的制造级别的第一组特征对准到包括形成在衬底中的高原子重量层并且使用电子束光刻形成第一组特征的电子束对准靶的方法， 将集成电路芯片的相同制造级别的特征集合到形成在基板中的光学对准目标并且使用光刻形成第二组特征，所述光学对准目标本身与电子束对准目标对准。 还有一种形成电子束对准靶的方法和结构。

公开(公告)号：US20080157260A1

公开(公告)日：2008-07-03

申请号：US11618974

申请日：2007-01-02

申请人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

发明人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

IPC分类号： H01L23/544 ,  G03F7/20 ,  H01L21/76

CPC分类号： G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

摘要翻译： 一种用于将集成电路芯片的制造级别的第一组特征对准到包括形成在衬底中的高原子重量层并且使用电子束光刻形成第一组特征的电子束对准靶的方法， 将集成电路芯片的相同制造级别的特征集合到形成在基板中的光学对准目标并且使用光刻形成第二组特征，所述光学对准目标本身与电子束对准目标对准。 还有一种形成电子束对准靶的方法和结构。