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公开(公告)号：US06968415B2
公开(公告)日：2005-11-22
申请号：US10113299
申请日：2002-03-29
CPC分类号： G06F13/4059
摘要： An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.
摘要翻译： 用于I / O适配器的桥的不透明的存储器区域。 不透明的存储器区域无法通过从主总线到次总线或辅助总线到主总线的桥接器的存储器事务。 因此，桥接器忽略了针对不透明存储器区域的内存事务，允许在每个存储不同数据的网桥两侧存在相同的地址。 不透明存储器区域的实现提供了在I / O适配器子系统存储器内完成存储器事务的手段，因此减轻了主机计算机系统存储器资源。 此外，主机和所有I / O设备使用一些相同的内存地址的主机系统中可以使用多个I / O适配器。
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2.发明授权公开(公告)号：US06985990B2
公开(公告)日：2006-01-10
申请号：US10114020
申请日：2002-03-29
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： Private devices are implemented on the secondary interface of PCI bridge by re-routing the activation of device select signals (IDSEL) during the address phase of a Type 0 configuration operation on the secondary bus in response to a Type 1 configuration operation on its primary bus. Under control of a mask register and device select reroute circuit, if a configuration command on the primary interface attempts to activate the IDSEL line associated with one of the private, or reroute, devices on the secondary interface, a different IDSEL is activated to select a monitoring device on the secondary interface.
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公开(公告)号：US06973528B2
公开(公告)日：2005-12-06
申请号：US10153041
申请日：2002-05-22
CPC分类号： G06F12/0862 , G06F12/0875 , G06F13/4027 , G06F2212/303 , G06F2212/6022
摘要： To prevent data performance impacts when dealing with target devices that can only transfer data for a limited number of bytes before disconnecting, the invention implements a short term data cache on the bridge. Using this feature, the bridge will cache additional data beyond a predetermined quantity of data following a disconnect with the requesting device. As such, the bridge may continue to prefetch additional data up to an amount specified by a prefetch read byte count and return the additional data should the requesting device request additional data resuming at the point of disconnect. However, the bridge will discard the additional data when at least one of the following occurs: a) the requesting device disconnects data transfer, and b) a further READ request that resumes at the point of disconnect is not received within a predetermined time.
摘要翻译： 为了防止在断开连接之前只能传输有限数量字节的数据的目标设备的数据性能影响，本发明实现了桥上的短期数据高速缓存。 使用此功能，桥接器将在与请求设备断开连接之后缓存超出预定数量的数据的附加数据。 因此，桥接器可以继续预取附加数据，直到预取读字节计数指定的量，并且如果请求设备在断开点请求附加数据恢复请求返回附加数据。 然而，当发生以下至少一个时，桥将丢弃附加数据：a）请求设备断开数据传输，并且b）在预定时间内没有接收到在断开点恢复的另一个READ请求。
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4.发明授权Processor, data processing system and method supporting a shared global coherency state 失效处理器，数据处理系统和支持共享全局一致性状态的方法公开(公告)号：US08495308B2
公开(公告)日：2013-07-23
申请号：US11539694
申请日：2006-10-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0817
摘要： A multiprocessor data processing system includes at least first and second coherency domains, where the first coherency domain includes a system memory and a cache memory. According to a method of data processing, a cache line is buffered in a data array of the cache memory and a state field in a cache directory of the cache memory is set to a coherency state to indicate that the cache line is valid in the data array, that the cache line is held in the cache memory non-exclusively, and that another cache in said second coherency domain may hold a copy of the cache line.
摘要翻译： 多处理器数据处理系统至少包括第一和第二相干域，其中第一相干域包括系统存储器和高速缓冲存储器。 根据数据处理的方法，将高速缓存行缓冲在高速缓冲存储器的数据阵列中，高速缓冲存储器的高速缓存目录中的状态字段被设置为一致性状态，以指示高速缓存行在数据中是有效的 数组，高速缓存存储器行被非排他地保存在高速缓冲存储器中，并且所述第二相干域中的另一个高速缓冲存储器可以保存高速缓存行的副本。
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公开(公告)号：US08312220B2
公开(公告)日：2012-11-13
申请号：US12420933
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/12
摘要： In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.
摘要翻译： 响应于多个处理单元中的第一处理单元的数据请求，第一处理单元从第一处理单元的较低级高速缓存中选择要丢弃的牺牲高速缓存行，并且确定是否设置了模式。 如果不是，则第一处理单元在互连结构上发出识别受害者高速缓存行的LCO命令，并指示较低级别的高速缓存是预期的目的地。 如果模式被设置，则第一处理单元发出具有替代预定目的地的停顿命令。 响应于指示LCO命令成功的LCO命令的一致性响应，第一处理单元从其较低级高速缓存中去除受害者高速缓存行，并且将受害者高速缓存行保持在数据处理系统的其他地方。 该模式可以设置为抑制系统内存的丢弃，例如进行测试。
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公开(公告)号：US08291259B2
公开(公告)日：2012-10-16
申请号：US12424412
申请日：2009-04-15
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/073 , G06F11/076 , G06F11/1064 , G06F12/0802 , G06F12/126
摘要： A processing unit includes a processor core and a cache memory coupled to the processor core. The cache memory includes a data array, a directory of the data array, error detection logic that sequentially detects a first, second and third correctable errors in the data array of the cache memory and provides indications of detection of the first, second and third correctable errors, and control circuitry that, responsive to the indication of the third correctable error and an indication that the first and second correctable errors occurred at too high a frequency, marks an entry of the data array containing a cache line having the third correctable error as deleted in the directory of the cache memory regardless of which entry of the data array contains a cache line having the second correctable error.
摘要翻译： 处理单元包括处理器核心和耦合到处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的目录，错误检测逻辑，其顺序地检测高速缓冲存储器的数据阵列中的第一，第二和第三可校正错误，并提供第一，第二和第三可校正的检测指示 错误和控制电路，其响应于第三可校正错误的指示和第一和第二可校正错误在太高频率处发生的指示，将包含具有第三可校正错误的高速缓存行的数据阵列的条目标记为 在高速缓冲存储器的目录中被删除，而不管数据阵列的哪个条目包含具有第二可校正错误的高速缓存行。
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公开(公告)号：US08209489B2
公开(公告)日：2012-06-26
申请号：US12256064
申请日：2008-10-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897 , Y02D10/13
摘要： A processing unit for a multiprocessor data processing system includes a processor core and a cache hierarchy coupled to the processor core to provide low latency data access. The cache hierarchy includes an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache. In response to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system.
摘要翻译： 用于多处理器数据处理系统的处理单元包括处理器核心和耦合到处理器核心的高速缓存层级以提供低延迟数据访问。 高速缓存层级包括耦合到处理器核心的高级缓存和耦合到高级缓存的较低级别的牺牲缓存。 响应于在高级缓存中丢失的处理器核心的预取请求，较低级别的受害者缓存确定预取请求是否丢失在较低级别的受害者缓存的目录中，并且如果是，则在下级缓存中分配状态机 通过向多处理器数据处理系统的至少一个其他处理单元发出预取请求来服务于预取请求。
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公开(公告)号：US20100268984A1
公开(公告)日：2010-10-21
申请号：US12424412
申请日：2009-04-15
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/073 , G06F11/076 , G06F11/1064 , G06F12/0802 , G06F12/126
摘要： A processing unit includes a processor core and a cache memory coupled to the processor core. The cache memory includes a data array, a directory of the data array, error detection logic that sequentially detects a first, second and third correctable errors in the data array of the cache memory and provides indications of detection of the first, second and third correctable errors, and control circuitry that, responsive to the indication of the third correctable error and an indication that the first and second correctable errors occurred at too high a frequency, marks an entry of the data array containing a cache line having the third correctable error as deleted in the directory of the cache memory regardless of which entry of the data array contains a cache line having the second correctable error.
摘要翻译： 处理单元包括处理器核心和耦合到处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的目录，错误检测逻辑，其顺序地检测高速缓冲存储器的数据阵列中的第一，第二和第三可校正错误，并提供第一，第二和第三可校正的检测指示 错误和控制电路，其响应于第三可校正错误的指示和第一和第二可校正错误在太高频率处发生的指示，将包含具有第三可校正错误的高速缓存行的数据阵列的条目标记为 在高速缓冲存储器的目录中被删除，而不管数据阵列的哪个条目包含具有第二可校正错误的高速缓存行。
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9.发明申请Empirically Based Dynamic Control of Transmission of Victim Cache Lateral Castouts 有权基于经验的动态控制受害者缓存横向铸件传动公开(公告)号：US20100262778A1
公开(公告)日：2010-10-14
申请号：US12421180
申请日：2009-04-09
申请人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0862 , G06F12/127 , G06F2212/6026
摘要： In response to a data request, a victim cache line is selected for castout from a lower level cache, and a target lower level cache of one of the plurality of processing units is selected. A determination is made whether the selected target lower level cache has provided more than a threshold number of retry responses to lateral castout (LCO) commands of the first lower level cache, and if so, a different target lower level cache is selected. The first processing unit thereafter issues a LCO command on the interconnect fabric. The LCO command identifies the victim cache line to be castout and indicates that the target lower level cache is an intended destination of the victim cache line. In response to a successful coherence response to the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译： 响应于数据请求，选择从较低级别高速缓冲存储器进行丢弃的受害者高速缓存行，并且选择多个处理单元之一的目标下级高速缓存。 确定所选择的目标下层高速缓存是否为第一较低级别高速缓存的横向转移（LCO）命令提供了超过阈值数量的重试响应，如果是，则选择不同的目标低级高速缓存。 此后，第一处理单元在互连结构上发出LCO命令。 LCO命令标识要丢弃的受害者缓存行，并指示目标下级缓存是受害缓存行的预期目标。 响应于对LCO命令的成功的一致性响应，从第一低级缓存中移除受害者高速缓存行并保存在第二较低级缓存中。
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10.发明授权Formation of an exclusive ownership coherence state in a lower level cache upon replacement from an upper level cache of a cache line in a private shared owner state 有权在私有共享所有者状态下从高速缓存行的高级缓存替换时，在下级缓存中形成独占所有权一致性状态公开(公告)号：US09110808B2
公开(公告)日：2015-08-18
申请号：US12649725
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
CPC分类号： G06F12/0811 , G06F9/3834 , G06F12/0815 , G06F12/0831 , Y02D10/13
摘要： In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hierarchy and retains a copy in a shared coherence state. The upper level cache holds the copy of the target cache line in a private shared ownership coherence state indicating that each cached copy of the target memory block is cached within the vertical cache hierarchy associated with the processor core. In response to the upper level cache signaling replacement of the copy of the target cache line in the private shared ownership coherence state, the lower level cache updates its copy of the target cache line to the exclusive ownership coherence state without coherency messaging with other vertical cache hierarchies.
摘要翻译： 响应于针对目标高速缓存线的处理器核心的存储器访问请求，与处理器核心相关联的垂直高速缓存层级的较低级缓存将目标高速缓存行的副本提供给垂直高速缓存层级中的高级缓存 并保留共享一致状态的副本。 高级缓存将目标高速缓存行的副本保存在私有共享所有权一致状态中，指示目标存储器块的每个高速缓存副本被缓存在与处理器核心相关联的垂直高速缓存层级内。 响应于在私有共享所有权相干状态下高级缓存信令替换目标高速缓存行的副本，下级缓存将其目标高速缓存行的副本更新为独占所有权相干状态，而不与其他垂直高速缓存的一致性消息传递 层次结构。
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