摘要:
A design structure for an apparatus for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs, is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.
摘要:
A mechanism for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.
摘要:
A mechanism for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.
摘要:
A design structure for an apparatus for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs, is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.
摘要:
A design structure embodied in a machine readable medium used in a design process includes an interleaved voltage-controlled oscillator, including a ring circuit of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in communication with the temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; and a DC offset generator configured to adjust the voltage of the amplified voltage signal.
摘要:
A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.
摘要:
Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.
摘要:
A hybrid phase locked loop (PLL) circuit for obtaining stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.
摘要:
A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.
摘要:
An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance. A chip level built-in circuit automatically calibrates the duty cycle correction (DCC) circuit setting for each chip. The chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. A built-in self-test provides results, i.e. pass or fail, of an array to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.