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公开(公告)号：US06526465B1
公开(公告)日：2003-02-25
申请号：US09324635
申请日：1999-06-02
申请人： David W. Voth , Ray A. Bittner, Jr.
发明人： David W. Voth , Ray A. Bittner, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/409 , H05K1/18
摘要： A computer system includes a centerplane formed by a printed circuit board. The centerplane has a plurality of Desktop PCI electrical connectors on one side and a plurality of CompactPCI electrical connectors on the other. This allows the use of both Desktop and CompactPCI boards in a signal bus board, without requiring complex bridging circuits. In addition, this allows additional boards to be used without extending the length of the PCI bus.
摘要翻译： 计算机系统包括由印刷电路板形成的中心面。 中心面在一侧具有多个Desktop PCI电连接器，另一侧具有多个CompactPCI电连接器。 这允许在信号总线板中使用Desktop和CompactPCI板，而不需要复杂的桥接电路。 此外，这允许在不延长PCI总线长度的情况下使用额外的电路板。
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公开(公告)号：US06883171B1
公开(公告)日：2005-04-19
申请号：US09324905
申请日：1999-06-02
CPC分类号： G06F13/4027
摘要： A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.
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公开(公告)号：US08896455B2
公开(公告)日：2014-11-25
申请号：US13334057
申请日：2011-12-22
申请人： Kenneth Eguro , Alessandro Forin , Ray A. Bittner, Jr. , Ji Sun
发明人： Kenneth Eguro , Alessandro Forin , Ray A. Bittner, Jr. , Ji Sun
CPC分类号： G06F21/554 , G06F21/86 , G06F2221/2101 , H04L63/1425
摘要： An intrusion detection system disclosed herein includes a detector circuit that measures a change in value of impedance of an interconnection circuitry. A decoder coupled to the detector decodes the measured value of the change in the impedance of the interconnection circuitry to determine existence of an abnormal condition. In an example implementation of the intrusion detection system, the change in the value of the impedance of the interconnection circuitry is represented by a change in the phase delay on the interconnection circuitry. An implementation of the intrusion detection circuit terminates communication using the interconnection circuitry upon detection of the abnormal condition. The intrusion detection system is further configured to interpret the abnormal condition as a communication signal to the interconnection circuitry.
摘要翻译： 本文公开的入侵检测系统包括检测器电路，其测量互连电路的阻抗值的变化。 耦合到检测器的解码器解码互连电路的阻抗的变化的测量值，以确定异常状况的存在。 在入侵检测系统的示例实现中，互连电路的阻抗值的变化由互连电路上的相位延迟的变化来表示。 入侵检测电路的实现在检测到异常情况时终止使用互连电路的通信。 入侵检测系统还被配置为将异常状况解释为互连电路的通信信号。
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公开(公告)号：US07260732B1
公开(公告)日：2007-08-21
申请号：US10900770
申请日：2004-07-28
申请人： Ray A. Bittner, Jr.
发明人： Ray A. Bittner, Jr.
CPC分类号： G06F1/26 , G06F1/28 , G06F1/3203
摘要： A power regulating system and method are provided for regulating power in a portable computing device. The portable computing device includes microprocessing and radio communication capabilities. The power regulating system utilizes a number of power states to regulate the device's internal power source voltage. The power regulating system operates to selectively control and regulate the device's internal power consumption based on the power state of the device, and thereby extends the useful life of the device by prolonging the battery life of the device.
摘要翻译： 提供了用于调节便携式计算设备中的功率的功率调节系统和方法。 便携式计算设备包括微处理和无线电通信能力。 功率调节系统利用多种功率状态来调节器件的内部电源电压。 功率调节系统基于设备的功率状态选择性地控制和调节设备的内部功耗，从而通过延长设备的电池寿命来延长设备的使用寿命。
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公开(公告)号：US07539487B2
公开(公告)日：2009-05-26
申请号：US11275489
申请日：2006-01-09
IPC分类号： H04M3/00
CPC分类号： H04M1/7253
摘要： A mobile server is wirelessly communicable with at least one remote input/output (I/O) device to form a wireless personal-area network (PAN). The mobile server has at least one application program interface (API) allowing an application of arbitrary implementation on the mobile server to recognize and control at least one service implemented by the remote I/O device.
摘要翻译： 移动服务器与至少一个远程输入/输出（I / O）设备无线通信，以形成无线个人区域网络（PAN）。 移动服务器具有允许在移动服务器上应用任意实现的至少一个应用程序接口（API）来识别和控制由远程I / O设备实现的至少一个服务。
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6.发明授权Worm-hole run-time reconfigurable processor field programmable gate array (FPGA) 失效蠕虫运行时可重构处理器现场可编程门阵列（FPGA）
公开(公告)号：US5828858A
公开(公告)日：1998-10-27
申请号：US714348
申请日：1996-09-16
申请人： Peter Athanas , Ray A. Bittner, Jr.
发明人： Peter Athanas , Ray A. Bittner, Jr.
IPC分类号： G06F15/173 , G06F15/177
CPC分类号： G06F15/7867 , G06F15/17343 , G06F15/17381
摘要： Higher performance is gained through a new architecture which implements a new method of computational resource allocation, utilization and programming based on the concept of Worm-hole Run-Time Reconfiguration (RTR). A stream-driven Worm-hole RTR methodology extends contemporary data-flow paradigms to utilize the dynamic creation of operators and pathways, based upon stream processing in which parcels of data move through custom created pathways and interact with other parcels to achieve the desired computation. These parcels independently allocate the necessary computing resources and data paths as they navigate through the platform. The Worm-hole RTR platform consists of a large number of configurable functional units that perform the custom computations and rich, configurable interconnection pathways between the functional units. Once a computational pathway has been established (sensitized) by the head of the stream parcel, data are processed through the pathway with zero overhead. All ports entering the computing platform serve both to configure operations and pathways and to pass computational data streams. As a result, programming and configuration is not limited to a single port. Configuration through multiple independent ports allows greater concurrency, faster reconfiguration, and fewer computational dependencies, all with relatively low cost in silicon.
摘要翻译： 通过一种基于蠕虫孔运行时重配置（RTR）概念实现计算资源分配，利用和编程的新方法的新架构获得了更高的性能。 基于流驱动的蠕虫孔RTR方法扩展了当前的数据流范式，以利用动态创建操作符和路径，基于流处理，其中数据包移动通过自定义创建的路径并与其他包裹进行交互以实现所需的计算。 这些包裹在他们浏览平台时独立地分配必要的计算资源和数据路径。 蠕虫RTR平台由大量可配置的功能单元组成，可执行定制计算和功能单元之间丰富，可配置的互连通路。 一旦计算路径已被流包裹的头部建立（敏感），数据就会以零开销通过路径进行处理。 进入计算平台的所有端口都可以配置操作和路径，并传递计算数据流。 因此，编程和配置不限于单个端口。 通过多个独立端口配置允许更大的并发性，更快的重新配置和更少的计算依赖性，所有这些都具有相对较低的硅成本。
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公开(公告)号：US08595220B2
公开(公告)日：2013-11-26
申请号：US12816689
申请日：2010-06-16
CPC分类号： G06F17/30011 , G06F17/24 , G06F17/3053 , G06F17/30598 , G06F17/30719 , G06Q30/02
摘要： One or more techniques and/or systems are provided for creating socially authored, or community authored, summaries of documents and/or for navigating a forum comprising such summaries. In one embodiment, at least some of the summaries are generated automatically when a document is written and/or discovered (e.g., by a web crawler), for example. In another embodiment, the documents are created by users of the forum. A plurality of summaries of a document may be created (e.g., by different users), and users can provide feedback, such as comments or ratings, that may assist other users in identifying which summary or summaries better describe the document. Moreover, the users can navigate the forum and retrieve summaries by browsing categories (and subcategories) to identify a topic of interest and/or by performing a search based upon user inputted search term(s).
摘要翻译： 提供一个或多个技术和/或系统用于创建社会创作或社区撰写的文档摘要和/或用于导航包括这样的摘要的论坛。 在一个实施例中，例如，当文档被写入和/或发现时（例如，通过网络爬虫）自动生成至少一些摘要。 在另一个实施例中，文档由论坛的用户创建。 可以创建文档的多个摘要（例如，由不同的用户），并且用户可以提供可以帮助其他用户识别哪些摘要或摘要更好地描述文档的反馈，例如评论或评级。 此外，用户可以浏览论坛并通过浏览类别（和子类别）来检索摘要，以识别感兴趣的主题和/或通过基于用户输入的搜索词进行搜索。
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公开(公告)号：US07856635B2
公开(公告)日：2010-12-21
申请号：US11082334
申请日：2005-03-17
CPC分类号： G06F13/4027
摘要： A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.
摘要翻译： 多任务操作系统和方法更新扩展寄存器中的PCI地址值，以确保各种线程在访问外围PCI设备时使用正确的值。 当应用程序线程需要访问PCI设备时，操作系统将PCI设备地址的高位位写入两个位置：（1）PCI主桥的扩展寄存器，以允许PCI设备的即时寻址，以及（ 2）与线程相关联的单独内存位置。 当从第一个线程发生到第二个线程的上下文切换时，操作系统从与第二个线程相关联的存储器位置检索存储的值，并将该值写入扩展寄存器。 以这种方式，当第二线程需要访问其PCI设备时，适当的地址值已经位于扩展寄存器中。
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公开(公告)号：US07793040B2
公开(公告)日：2010-09-07
申请号：US11143060
申请日：2005-06-01
申请人： Ray A. Bittner, Jr.
发明人： Ray A. Bittner, Jr.
CPC分类号： G06F12/0895
摘要： A content addressable memory (CAM) architecture comprises two components, a small, fast on-chip cache memory that stores data that is likely needed in the immediate future, and an off-chip main memory in normal RAM. The CAM allows data to be stored with an associated tag that is of any size and identifies the data. Via tags, waves of data are launched into a machine's computational hardware and re-associated with related tags upon return. Tags may be generated so that related data values have adjacent storage locations, facilitating fast retrieval. Typically, the CAM emits only complete operand sets. By using tags to identify unique operand sets, computations can be allowed to proceed out of order, and be recollected later for further processing. This allows greater computational speed via multiple parallel processing units that compute large sets of operand sets, or by opportunistically fetching and executing operand sets as they become available.
摘要翻译： 内容可寻址存储器（CAM）架构包括两个组件，即存储在不久的将来可能需要的数据的小型，快速的片上高速缓存存储器和正常RAM中的片外主存储器。 CAM允许使用任何大小的关联标签存储数据并识别数据。 通过标签，数据波发射到机器的计算硬件中，并在返回时与相关标签重新关联。 可以生成标签，使得相关数据值具有相邻的存储位置，便于快速检索。 通常，CAM仅发出完整的操作数集。 通过使用标签来识别唯一的操作数集合，可以允许计算继续执行，并且稍后重新进行进一步处理。 这允许通过计算大组操作数集合的多个并行处理单元或通过机会地获取和执行操作数集合使其变得可用时更大的计算速度。
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公开(公告)号：US06434647B1
公开(公告)日：2002-08-13
申请号：US09321478
申请日：1999-05-27
申请人： Ray A. Bittner, Jr.
发明人： Ray A. Bittner, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/4086
摘要： A PCI reflected-wave communications bus has a plurality of individual signal lines. Each signal line is terminated with a resistive-capacitive filter to partially dampen voltage wave reflections.
摘要翻译： PCI反射波通信总线具有多个单独的信号线。 每个信号线用电阻电容滤波器终止，以部分抑制电压波反射。
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