公开(公告)号：US08329519B2

公开(公告)日：2012-12-11

申请号：US13305449

申请日：2011-11-28

Applicant: Zhonghai Shi ,  David Wu ,  Mark Michael ,  Donna Michael, legal representative

Inventor： Zhonghai Shi ,  David Wu ,  Mark Michael

IPC: H01L27/12

CPC classification number: H01L29/41733 ,  H01L21/28518 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Abstract translation: 提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。 这些半导体器件包括半导体器件结构和接触。 在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

公开(公告)号：US07598161B2

公开(公告)日：2009-10-06

申请号：US11861534

申请日：2007-09-26

Applicant: Jingrong Zhou ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Akif Sultan

Inventor： Jingrong Zhou ,  Mark Michael ,  David Wu ,  James F. Buller ,  Akif Sultan

IPC: H01L21/425

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083

Abstract: The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

Abstract translation: 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。 创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

公开(公告)号：US07271047B1

公开(公告)日：2007-09-18

申请号：US11327641

申请日：2006-01-06

Applicant: Jianhong Zhu ,  Mark Michael ,  David Wu

Inventor： Jianhong Zhu ,  Mark Michael ,  David Wu

IPC: H01L21/8238

CPC classification number: H01L22/34 ,  H01L22/14

Abstract: A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.

Abstract translation: 提供了测试结构及其使用和制造方法。 在一个方面，提供一种测试结构，其包括具有第一端和第二导体的第一导体，第二导​​体具有位于第一端上方的第二端。 第三导体位于第一导体的第一端和第二导体的第二端之间。 第一电极以距离第三导体第一距离的第一导体耦合到第一导体，第二电极以距离第三导体第二距离的方式耦合到第一导体。 第三电极以距离第三导体第三距离的方式耦合到第二导体，并且第四电极在距离第三导体的第四距离处耦合到第二导体。 第一至第四电极提供电压检测抽头，并且第一和第二导体提供电流检测抽头，从该第三导体提供第三导体的电阻。

公开(公告)号：US07761838B2

公开(公告)日：2010-07-20

申请号：US11861492

申请日：2007-09-26

Applicant: Zhonghai Shi ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

Inventor： Zhonghai Shi ,  Mark Michael ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

IPC: G06F17/50 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/78 ,  H01L29/7843

Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Abstract translation: 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

公开(公告)号：US07638837B2

公开(公告)日：2009-12-29

申请号：US11861051

申请日：2007-09-25

Applicant: Akif Sultan ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu

Inventor： Akif Sultan ,  Mark Michael ,  David Wu

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

Abstract: A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

Abstract translation: 提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。 有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。 第二类应力层设置在活动区域​​的第二侧边缘附近。

公开(公告)号：US08134208B2

公开(公告)日：2012-03-13

申请号：US11861928

申请日：2007-09-26

Applicant: Zhonghai Shi ,  David Wu ,  Mark Michael ,  Donna Michael, legal representative

Inventor： Zhonghai Shi ,  David Wu ,  Mark Michael

IPC: H01L27/12

CPC classification number: H01L29/41733 ,  H01L21/28518 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Abstract translation: 提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。 这些半导体器件包括半导体器件结构和接触。 在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

公开(公告)号：US20090078998A1

公开(公告)日：2009-03-26

申请号：US11861928

申请日：2007-09-26

Applicant: Zhongai Shi ,  David Wu ,  Mark Michael ,  Donna Michael

Inventor： Zhongai Shi ,  David Wu ,  Mark Michael ,  Donna Michael

IPC: H01L23/48 ,  H01L21/4763 ,  H01L27/01

CPC classification number: H01L29/41733 ,  H01L21/28518 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Abstract translation: 提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。 这些半导体器件包括半导体器件结构和接触。 在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

公开(公告)号：US20070259513A1

公开(公告)日：2007-11-08

申请号：US11381219

申请日：2006-05-02

Applicant: David Wu ,  Mark Michael

Inventor： David Wu ,  Mark Michael

IPC: H01L21/44

CPC classification number: H01L21/76819 ,  H01L21/76802 ,  H01L21/76834 ,  H01L29/7843

Abstract: The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature above a semiconducting substrate, forming a layer stack comprised of a plurality of layers of material above the feature, the layer stack having an original height, reducing the original height of the layer stack to thereby define a reduced height layer stack above the feature, forming an opening in the reduced height layer stack for a conductive member that will be electrically coupled to the feature and forming the conductive member in the opening in the reduced height layer stack.

Abstract translation: 本发明涉及形成接触开口的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成特征，形成由特征上方的多层材料构成的层叠层，层堆叠具有原始高度，从而降低层堆叠的原始高度 在所述特征之上限定减小的高度层堆叠，在所述减小的高度层堆叠中形成用于导电构件的开口，所述导电构件将电耦合到所述特征并且在所述还原高度层堆叠中的所述开口中形成所述导电构件。

公开(公告)号：US07704320B2

公开(公告)日：2010-04-27

申请号：US10838908

申请日：2004-05-03

Applicant: David W. M. Marr ,  Tieying Gong ,  David Wu

Inventor： David W. M. Marr ,  Tieying Gong ,  David Wu

IPC: C30B30/04

CPC classification number: C30B7/00 ,  C30B29/54

Abstract: The methods provided use external fields such as light and electricity as a means of directing the crystallization of concentrated colloidal systems. Not only can nucleation be directed, crystal melting can be carefully controlled and light-induced crystal diffraction used as a means of directing light propagation. A number of factors play a significant role on the crystallization rate and location, including the intensity of the light field, the magnitude of the electric field, the colloid concentration, the colloid size, and the colloid composition. In varying these parameters, kinetics in these processes are extremely fast when compared to traditional colloidal crystallization approaches.

Abstract translation: 提供的方法使用诸如光和电的外部领域作为指导浓缩胶体体系的结晶的手段。 成核不仅可以引导，晶体熔化也可以小心控制，光诱导的晶体衍射用作引导光传播的手段。 许多因素对结晶速率和位置都起着重要的作用，包括光场强度，电场强度，胶体浓度，胶体尺寸和胶体组成。 在改变这些参数时，与传统的胶体结晶方法相比，这些方法中的动力学非常快。

公开(公告)号：US20080165199A1

公开(公告)日：2008-07-10

申请号：US11621917

申请日：2007-01-10

Applicant: Jian Wei ,  James M. Brown ,  David Wu

Inventor： Jian Wei ,  James M. Brown ,  David Wu

IPC: G06T1/20

CPC classification number: G06T15/005 ,  G06T1/20

Abstract: A device has a processor for processing a vertex processing stage, a sub-screen dividing stage and a pixel rendering stage of a three-dimensional (3D) graphics pipeline. The processor includes processing threads which balance the work load of the 3D graphics pipeline by prioritizing processing for the pixel rendering stage over other stages. Each processing thread, operating in parallel and independently, checks a level of tasks in a Task list of sub-screen tasks. If the level is below a threshold value, empty or the sub-screen tasks are all locked, the processing thread loops to the vertex processing stage. Otherwise, the processing thread processes a sub-screen task during the pixel rendering stage.

Abstract translation: 一种设备具有用于处理三维（3D）图形流水线的顶点处理阶段，子屏幕划分阶段和像素渲染阶段的处理器。 该处理器包括处理线程，其平衡3D图形流水线的工作负载，通过对像素渲染阶段的处理优先于其他阶段。 并行和独立运行的每个处理线程检查子屏幕任务的任务列表中的任务级别。 如果该级别低于阈值，则清空或子屏幕任务都被锁定，则处理线程循环到顶点处理阶段。 否则，处理线程在像素渲染阶段处理子屏幕任务。