IMAGE SENSOR WITH TOLERANCE OPTIMIZING INTERCONNECTS

    公开(公告)号:US20220031154A1

    公开(公告)日:2022-02-03

    申请号:US17505419

    申请日:2021-10-19

    发明人: Laurent Blanquart

    摘要: Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

    IMAGE SENSOR WITH TOLERANCE OPTIMIZING INTERCONNECTS

    公开(公告)号:US20200146542A1

    公开(公告)日:2020-05-14

    申请号:US16747116

    申请日:2020-01-20

    发明人: Laurent Blanquart

    摘要: Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.