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    Non-volatile storage with compensation for source voltage drop
    3.
    发明授权
    Non-volatile storage with compensation for source voltage drop 有权
    非易失性存储器，用于补偿源电压降

    公开(公告)号：US07606072B2

    公开(公告)日：2009-10-20

    申请号：US11739509

    申请日：2007-04-24

    申请人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

    发明人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

    IPC分类号： G11C16/06

    CPC分类号： G11C8/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3436

    摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

    摘要翻译： 解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。 在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。 在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。 也可以使用这些方法的各种组合。 在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。 还可以补偿向前的身体偏差。

    Non-Volatile Memory with Compensation for Variations Along a Word Line
    4.
    发明申请
    Non-Volatile Memory with Compensation for Variations Along a Word Line 有权
    具有补偿的非易失性存储器，沿着字线变化

    公开(公告)号：US20080239824A1

    公开(公告)日：2008-10-02

    申请号：US11693616

    申请日：2007-03-29

    申请人： Deepak Chandra Sekar ,  Man Lung Mui ,  Nima Mokhlesi

    发明人： Deepak Chandra Sekar ,  Man Lung Mui ,  Nima Mokhlesi

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/12

    摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage.

    摘要翻译： 由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来补偿编程速率。 以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程效率的变化显着降低。 这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。 在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被设置为第一电压，并且存储器平面的后半部分中的位线远离字源 线电压被设定为第二电压。

    Compensating source voltage drop in non-volatile storage
    5.
    发明授权
    Compensating source voltage drop in non-volatile storage 有权
    在非易失性存储器中补偿电源电压降

    公开(公告)号：US07606071B2

    公开(公告)日：2009-10-20

    申请号：US11739501

    申请日：2007-04-24

    申请人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

    发明人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

    IPC分类号： G11C16/06

    CPC分类号： G11C8/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3436

    摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

    摘要翻译： 解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。 在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。 在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。 也可以使用这些方法的各种组合。 在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。 还可以补偿向前的身体偏差。

    COMPENSATING SOURCE VOLTAGE DROP IN NON-VOLATILE STORAGE
    7.
    发明申请
    COMPENSATING SOURCE VOLTAGE DROP IN NON-VOLATILE STORAGE 有权
    在非易失性存储中补偿电源电压

    公开(公告)号：US20080266963A1

    公开(公告)日：2008-10-30

    申请号：US11739501

    申请日：2007-04-24

    申请人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

    发明人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

    IPC分类号： G11C11/34

    CPC分类号： G11C8/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3436

    摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

    摘要翻译： 解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。 在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。 在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。 也可以使用这些方法的各种组合。 在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。 还可以补偿向前的身体偏差。

    Non-volatile memory with compensation for variations along a word line
    8.
    发明授权
    Non-volatile memory with compensation for variations along a word line 有权
    具有补偿沿字线变化的非易失性存储器

    公开(公告)号：US07577031B2

    公开(公告)日：2009-08-18

    申请号：US11693616

    申请日：2007-03-29

    申请人： Deepak Chandra Sekar ,  Man Lung Mui ,  Nima Mokhlesi

    发明人： Deepak Chandra Sekar ,  Man Lung Mui ,  Nima Mokhlesi

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/12

    摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage.

    摘要翻译： 由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来补偿编程速率。 以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程效率的变化显着降低。 这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。 在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被设置为第一电压，并且存储器平面的后半部分中的位线远离字源 线电压被设定为第二电压。

    Method of compensating variations along a word line in a non-volatile memory
    9.
    发明授权
    Method of compensating variations along a word line in a non-volatile memory 有权
    补偿非易失性存储器中字线变化的方法

    公开(公告)号：US07508713B2

    公开(公告)日：2009-03-24

    申请号：US11693601

    申请日：2007-03-29

    申请人： Deepak Chandra Sekar ,  Man Lung Mui ,  Nima Mokhlesi

    发明人： Deepak Chandra Sekar ,  Man Lung Mui ,  Nima Mokhlesi

    IPC分类号： G11C16/04

    CPC分类号： G11C8/08 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12

    摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.

    摘要翻译： 由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来补偿编程速率。 以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程效率的变化显着降低。 这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。 在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被第一电压移位器设置为第一电压，并且存储器平面的后半部分中的位线进一步 从第二电压转换器将字线电压源设定为第二电压。

    NON-VOLATILE STORAGE WITH COMPENSATION FOR SOURCE VOLTAGE DROP
    10.
    发明申请
    NON-VOLATILE STORAGE WITH COMPENSATION FOR SOURCE VOLTAGE DROP 有权
    具有补偿源电压下降的非易失性存储

    公开(公告)号：US20080266964A1

    公开(公告)日：2008-10-30

    申请号：US11739509

    申请日：2007-04-24

    申请人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

    发明人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

    IPC分类号： G11C11/34

    CPC分类号： G11C8/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3436

    摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

    摘要翻译： 解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。 在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。 在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。 也可以使用这些方法的各种组合。 在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。 还可以补偿向前的身体偏差。