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    Dual layer stress liner for MOSFETS
    1.
    发明授权
    Dual layer stress liner for MOSFETS 失效
    用于MOSFET的双层应力衬垫

    公开(公告)号：US07521308B2

    公开(公告)日：2009-04-21

    申请号：US11616147

    申请日：2006-12-26

    申请人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    发明人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

    摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

    摘要翻译： 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

    DUAL LAYER STRESS LINER FOR MOSFETS
    2.
    发明申请
    DUAL LAYER STRESS LINER FOR MOSFETS 失效
    用于MOSFET的双层应力衬垫

    公开(公告)号：US20080153217A1

    公开(公告)日：2008-06-26

    申请号：US11616147

    申请日：2006-12-26

    申请人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    发明人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

    摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

    摘要翻译： 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

    Structure of static random access memory with stress engineering for stability
    8.
    发明授权
    Structure of static random access memory with stress engineering for stability 有权
    具有应力工程稳定性的静态随机存取存储器的结构

    公开(公告)号：US07471548B2

    公开(公告)日：2008-12-30

    申请号：US11611569

    申请日：2006-12-15

    申请人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

    发明人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

    IPC分类号： G11C11/412 ,  H01L29/78

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

    摘要： An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.

    摘要翻译： 提供了一种集成电路（IC），其包括至少一个静态随机存取存储器（SRAM）单元，其中提高了SRAM单元的性能，但具有良好的稳定性和可写性。 特别地，本发明提供一种包括至少一个SRAM单元的IC，其中伽马比为约1或更大。 γ比值随着pFET器件性能的降低而增加。 更重要的是，在本发明的IC中，在SRAM区域中不存在应力衬垫边界，并且与常规SRAM结构相比，所有器件的离子变化都减小了。 本发明提供一种集成电路（IC），其包括至少一个包含至少一个nFET和至少一个pFET的SRAM单元; 以及位于nFET和pFET上方并与其相邻的连续松弛应力衬垫。

    STRESS ENGINEERING FOR SRAM STABILITY
    9.
    发明申请
    STRESS ENGINEERING FOR SRAM STABILITY 有权
    用于SRAM稳定性的应力工程

    公开(公告)号：US20080142895A1

    公开(公告)日：2008-06-19

    申请号：US11611569

    申请日：2006-12-15

    申请人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

    发明人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

    IPC分类号： H01L27/11

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

    摘要： An IC is provided that includes at least one SRAM cell in which the performance of the SRAM cell is enhanced, yet maintaining good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention, solves the above by providing an integrated circuit (IC) that comprises at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.

    摘要翻译： 提供了一种IC，其包括至少一个SRAM单元，其中SRAM单元的性能得到增强，同时保持良好的稳定性和可编写性。 特别地，本发明提供一种包括至少一个SRAM单元的IC，其中伽马比为约1或更大。 在本发明中，γ比随着pFET器件性能的降低而增加。 此外，在本发明的IC中，在SRAM区域中不存在应力衬垫边界，并且与常规SRAM结构相比，所有器件的离子变化都减小了。 本发明通过提供一种包括至少一个包括至少一个nFET和至少一个pFET的静态随机存取存储器的集成电路（IC）来解决上述问题， 以及位于所述至少一个nFET和所述至少一个pFET之上并邻接所述至少一个nFET的连续松弛应力衬垫。

    Overlapped stressed liners for improved contacts
    10.
    发明授权
    Overlapped stressed liners for improved contacts 失效
    重叠的应力衬垫改善了接触

    公开(公告)号：US07612414B2

    公开(公告)日：2009-11-03

    申请号：US11693254

    申请日：2007-03-29

    申请人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

    IPC分类号： H01L21/8238 ,  H01L23/18

    CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

    摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

    摘要翻译： 提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。 第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。 第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。 第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。 第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。