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    Overlapped stressed liners for improved contacts
    1.
    发明授权
    Overlapped stressed liners for improved contacts 失效
    重叠的应力衬垫改善了接触

    公开(公告)号：US07612414B2

    公开(公告)日：2009-11-03

    申请号：US11693254

    申请日：2007-03-29

    申请人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

    IPC分类号： H01L21/8238 ,  H01L23/18

    CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

    摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

    摘要翻译： 提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。 第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。 第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。 第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。 第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

    OVERLAPPED STRESSED LINERS FOR IMPROVED CONTACTS
    2.
    发明申请
    OVERLAPPED STRESSED LINERS FOR IMPROVED CONTACTS 失效
    用于改进联系人的超重压力衬管

    公开(公告)号：US20080237737A1

    公开(公告)日：2008-10-02

    申请号：US11693254

    申请日：2007-03-29

    申请人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

    IPC分类号： H01L29/76 ,  H01L21/8238

    CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

    摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

    摘要翻译： 提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。 第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。 第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。 第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。 第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

    STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET
    6.
    发明申请
    STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET 失效
    用于制造低漏电和低失真的NMOSFET的结构和方法

    公开(公告)号：US20110175170A1

    公开(公告)日：2011-07-21

    申请号：US12691183

    申请日：2010-01-21

    申请人： Xinlin Wang ,  Xiangdong Chen ,  Haining S. Yang

    发明人： Xinlin Wang ,  Xiangdong Chen ,  Haining S. Yang

    IPC分类号： H01L29/66 ,  H01L21/8238

    CPC分类号： H01L27/092 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104

    摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.

    摘要翻译： 公开了一种改进的SRAM和制造方法。 该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。 用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题 例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

    Semiconductor device structure having enhanced performance FET device
    7.
    发明授权
    Semiconductor device structure having enhanced performance FET device 有权
    具有增强型FET器件的半导体器件结构

    公开(公告)号：US07935993B2

    公开(公告)日：2011-05-03

    申请号：US12643482

    申请日：2009-12-21

    申请人： Xiangdong Chen ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Haining S. Yang

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823807 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench.

    摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成：在栅极上的第一层和栅极上的第二层，具有间隔物，与栅极相邻的源极和漏极区域，栅极上的硅化物和源极和漏极区域; 在由成形步骤导致的结构上设置应力层; 在应力层上设置绝缘层; 去除绝缘层的部分以暴露应力层的顶表面; 去除应力层的顶表面和其它部分和间隔物的部分以形成沟槽，然后将合适的应力材料设置到沟槽中。

    COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS
    8.
    发明申请
    COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS 有权
    具有嵌入式硅源和漏区的补充场效应晶体管

    公开(公告)号：US20090256173A1

    公开(公告)日：2009-10-15

    申请号：US12103301

    申请日：2008-04-15

    申请人： Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.

    摘要翻译： 提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。 在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。 第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。 基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。 可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。 基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。 然后可以在嵌入的硅区域中形成源区和漏区。 硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。

    Dual stress liner
    9.
    发明授权
    Dual stress liner 有权
    双重应力衬垫

    公开(公告)号：US07361539B2

    公开(公告)日：2008-04-22

    申请号：US11383560

    申请日：2006-05-16

    申请人： Xiangdong Chen ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Haining S. Yang

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L29/7842

    摘要： A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

    摘要翻译： 提供一种半导体器件结构，其包括第一场效应晶体管（“FET”），其具有第一沟道区，第一源极区，第一漏极区和覆盖第一沟道区的第一栅极导体。 包括第二FET，其具有覆盖第二沟道区的第二沟道区，第二源极区，第二漏极区和第二栅极导体。 第一和第二栅极导体是在第一和第二沟道区两者上延伸的单个细长导电构件的部分。 第一应力膜覆盖第一FET，第一应力膜将具有第一值的应力施加到第一沟道区。 第二应力膜覆盖第二FET，第二应力膜向第二沟道区施加具有第二值的应力。 第二个值与第一个值大不相同。 此外，第一和第二应力膜在共同边界处彼此邻接并且在共同边界处呈现基本上共平面的主表面。

    IMPROVED CMOS DEVICES WITH STRESSED CHANNEL REGIONS, AND METHODS FOR FABRICATING THE SAME
    10.
    发明申请
    IMPROVED CMOS DEVICES WITH STRESSED CHANNEL REGIONS, AND METHODS FOR FABRICATING THE SAME 有权
    改进的具有应力通道区域的CMOS器件及其制造方法

    公开(公告)号：US20080001182A1

    公开(公告)日：2008-01-03

    申请号：US11427495

    申请日：2006-06-29

    申请人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

    IPC分类号： H01L29/76 ,  H01L27/148

    CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

    摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.

    摘要翻译： 本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。 具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着 第二，不同组的等效晶面。 这种附加表面可以通过晶体蚀刻容易地形成。 此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。 这样的应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。