公开(公告)号：US20230078473A1

公开(公告)日：2023-03-16

申请号：US17932104

申请日：2022-09-14

申请人： Deliang Fan ,  Adnan Siraj Rakin ,  Li Yang ,  Chaitali Chakrabarti ,  Yu Cao ,  Jae-sun Seo ,  Jingtao Li

发明人： Deliang Fan ,  Adnan Siraj Rakin ,  Li Yang ,  Chaitali Chakrabarti ,  Yu Cao ,  Jae-sun Seo ,  Jingtao Li

IPC分类号： G06N3/08 ,  G06N3/04

摘要： A robust and accurate binary neural network, referred to as RA-BNN, is provided to simultaneously defend against adversarial noise injection and improve accuracy. Recently developed adversarial weight attack, a.k.a. bit-flip attack (BFA), has shown enormous success in compromising deep neural network (DNN) performance with an extremely small amount of model parameter perturbation. To defend against this threat, embodiments of RA-BNN adopt a complete binary neural network (BNN) to significantly improve DNN model robustness (defined as the number of bit-flips required to degrade the accuracy to as low as a random guess). To improve clean inference accuracy, a novel and efficient two-stage network growing method is proposed and referred to as early growth. Early growth selectively grows the channel size of each BNN layer based on channel-wise binary masks training with Gumbel-Sigmoid function. Apart from recovering the inference accuracy, the RA-BNN after growing also shows significantly higher resistance to BFA.

公开(公告)号：US09934463B2

公开(公告)日：2018-04-03

申请号：US15156113

申请日：2016-05-16

申请人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

发明人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

IPC分类号： G11C11/00 ,  G06N3/08 ,  G11C11/54 ,  G11C13/00

CPC分类号： G06N3/088 ,  G06N3/0635 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0069

摘要： Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

公开(公告)号：US09466362B2

公开(公告)日：2016-10-11

申请号：US14824782

申请日：2015-08-12

申请人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

发明人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

IPC分类号： G11C5/06 ,  G11C13/00

CPC分类号： G11C13/0026 ,  G11C5/06 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79

摘要： This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network.

摘要翻译： 本公开一般涉及电阻式存储器系统。 电阻式存储器系统可用于实现具有完全并行性的神经启发式学习算法。 在一个实施例中，电阻式存储器系统包括交叉点电阻网络和可切换路径。 交叉点电阻网络包括可变电阻元件和导线。 导线耦合到可变电阻元件，使得导线和可变电阻元件形成交叉电阻网络。 可切换路径连接到导线，使得可切换路径可操作以选择性地互连导电线组，使得可变电阻元件的子集各自提供组合的可变电导。 在子集中具有多个电阻元件，电阻元件的电导的工艺变化平均。 因此，可以使用交叉点电阻网络以更高的精度来实现学习算法。

公开(公告)号：US20160049195A1

公开(公告)日：2016-02-18

申请号：US14824782

申请日：2015-08-12

申请人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

发明人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

IPC分类号： G11C13/00

CPC分类号： G11C13/0026 ,  G11C5/06 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79

摘要： This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network.

摘要翻译： 本公开一般涉及电阻式存储器系统。 电阻式存储器系统可用于实现具有完全并行性的神经启发式学习算法。 在一个实施例中，电阻式存储器系统包括交叉点电阻网络和可切换路径。 交叉点电阻网络包括可变电阻元件和导线。 导线耦合到可变电阻元件，使得导线和可变电阻元件形成交叉电阻网络。 可切换路径连接到导线，使得可切换路径可操作以选择性地互连导电线组，使得可变电阻元件的子集各自提供组合的可变电导。 在子集中具有多个电阻元件，电阻元件的电导的工艺变化平均。 因此，可以使用交叉点电阻网络以更高的精度来实现学习算法。

公开(公告)号：US20160336064A1

公开(公告)日：2016-11-17

申请号：US15156113

申请日：2016-05-16

申请人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

发明人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

IPC分类号： G11C13/00 ,  G06N3/08

CPC分类号： G06N3/088 ,  G06N3/0635 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0069

摘要： Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

摘要翻译： 公开了包括交叉点电阻网络和线路控制电路的神经计算电路。 交叉点电阻网络包括可变电阻单元。 一组可变电阻单元被配置为在导线上产生校正线电流，而其他组的可变电阻单元在其它导线上产生合成线电流。 线路控制电路被配置为从导线接收线电流并产生数字矢量值。 根据对应的合成线电流的电流电平和校正线电流的电流电平之间的差，提供每个数字矢量值。 以这种方式，通过校正线电流的当前电平来校正数字矢量值，以便减少由有限导通到导通状态比率导致的误差。

公开(公告)号：US12004201B2

公开(公告)日：2024-06-04

申请号：US16992921

申请日：2020-08-13

申请人： Amine Maaref ,  Yu Cao ,  Yongxia Lyu ,  Jianglei Ma

发明人： Amine Maaref ,  Yu Cao ,  Yongxia Lyu ,  Jianglei Ma

IPC分类号： H04W72/04 ,  H04W72/02 ,  H04W72/044 ,  H04W72/12 ,  H04W72/23 ,  H04W72/30 ,  H04W72/51

CPC分类号： H04W72/51 ,  H04W72/02 ,  H04W72/044 ,  H04W72/23 ,  H04W72/30

摘要： A method for transmitting data over a SL data channel wherein a transmit UE and a receive UE are each semi-statically provided with a CG configuration such that a CG configuration indication does not have to be transmitted in association with each individual data transmission during a duration that the CG configuration is applied.

公开(公告)号：US11516826B2

公开(公告)日：2022-11-29

申请号：US16544274

申请日：2019-08-19

申请人： Yu Cao ,  Liqing Zhang ,  Jianglei Ma

发明人： Yu Cao ,  Liqing Zhang ,  Jianglei Ma

IPC分类号： H04W72/12 ,  H04L1/18 ,  H04W28/04 ,  H04W72/14 ,  H04W74/00 ,  H04L5/00 ,  H04W72/04 ,  H04L1/00

摘要： Methods and systems are provided for signaling for semi-static configuration in grant free uplink transmissions. Radio resource control (RRC) signaling is used to provide information from a base station to a user equipment (UE) that configure the grant free transmission resource to be used by the UE. In some implementations, the RRC signaling may be used in conjunction with system information that is transmitted to all UEs and/or Downlink Control Information (DCI) that the UE needs to access subsequent to the RRC signaling. In some implementations, the DCI includes an activation or deactivation indicator that the UE monitors to determine when the UE is allowed to transmit to the BS or should stop transmitting. Implementations allow for grant free transmission resources to be configured on an individual user based and a group basis.

公开(公告)号：US11044748B2

公开(公告)日：2021-06-22

申请号：US16392827

申请日：2019-04-24

申请人： Yu Cao ,  Amine Maaref ,  Jianglei Ma

发明人： Yu Cao ,  Amine Maaref ,  Jianglei Ma

IPC分类号： H04W72/14 ,  H04W4/40 ,  H04W72/12

摘要： A user equipment (UE) receives a message that indicates a sidelink (SL) communication resource configuration to be used by the UE for communicating SL control information and SL data between the UE and another UE. The UE transmits SL control information according to the SL communication resource configuration, and transmits SL data according to the SL communication resource configuration. The SL control information and the SL data are transmitted by the UE without the UE receiving, in a downlink control information (DCI), a grant of communication resources.

公开(公告)号：US10813124B2

公开(公告)日：2020-10-20

申请号：US16193365

申请日：2018-11-16

申请人： Yu Cao ,  Liqing Zhang ,  Jianglei Ma

发明人： Yu Cao ,  Liqing Zhang ,  Jianglei Ma

IPC分类号： H04W72/14 ,  H04L1/16 ,  H04W74/02 ,  H04L1/18 ,  H04W72/12 ,  H04W88/02 ,  H04W88/08

摘要： There may be situations in which it is beneficial for a user equipment to switch between grant-free uplink wireless transmissions and grant-based uplink wireless transmissions. Systems and methods are disclosed that help facilitate grant-based and grant-free uplink wireless communications, and the switching between the two. For example, systems and methods for mitigating collision between a granted uplink wireless transmission and a grant-free uplink wireless transmission are disclosed herein.

公开(公告)号：US10651980B2

公开(公告)日：2020-05-12

申请号：US16151920

申请日：2018-10-04

申请人： Yu Cao ,  Liqing Zhang

发明人： Yu Cao ,  Liqing Zhang

IPC分类号： H04L1/18 ,  H04L1/00

摘要： Systems and methods are disclosed for performing hybrid automatic repeat request (HARQ) for grant-free uplink transmissions. Some of the systems and methods disclosed herein may address problems such as how to perform acknowledgement (ACK) and/or negative acknowledgement (NACK), how to determine and signal retransmission timing, how to determine the transmission/retransmission attempt and the redundancy version (RV), and/or how to perform the HARQ combining.