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公开(公告)号：US08713249B2
公开(公告)日：2014-04-29
申请号：US13776295
申请日：2013-02-25
申请人： Dell Products, L.P.
发明人： Stuart Berke
CPC分类号： G06F13/1694
摘要： A memory system includes a first memory module and a second memory module. A memory controller is coupled to the first and second memory modules and reads configuration information from the first and second memory modules using a memory channel. The controller also configures a switch coupled between the controller and one of the memory modules to communicate using either a chip select line or a memory address line.
摘要翻译： 存储器系统包括第一存储器模块和第二存储器模块。 存储器控制器耦合到第一和第二存储器模块，并且使用存储器通道从第一和第二存储器模块读取配置信息。 控制器还配置一个开关，该开关耦合在控制器和其中一个存储器模块之间，以便使用芯片选择线或存储器地址线进行通信。
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公开(公告)号：US09250934B2
公开(公告)日：2016-02-02
申请号：US14149339
申请日：2014-01-07
申请人： Dell Products L.P.
发明人： Stuart Berke , William Sauber
CPC分类号： G06F9/44557 , G06F11/1016 , G06F13/409 , G11C5/04 , G11C5/14 , Y02D10/14 , Y02D10/151
摘要： An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.
摘要翻译： 一种装置，包括被配置为装配到处理系统中的第一插座中的第一连接器，所述第一连接器和第一插座符合第一标准，第二插座被配置为接纳其中的存储器模块，所述第二插座和所述存储器模块符合 第二标准，通信地耦合到第一连接器和第二插座的存储缓冲器模块，所述存储器缓冲模块被配置为从所述第一连接器接收与所述第一标准相关联的信号，并将与所述第二标准相关联的信号输出到所述第二插座，以及 虚拟化模块，其通信地耦合到所述存储器缓冲器模块，所述第一连接器和所述第二插座，所述虚拟化模块被配置为从所述第二插座接收与所述第二标准相关联的第一初始化数据，并将与所述第一标准相关联的第二初始化数据输出到 处理系统。
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公开(公告)号：US20140122966A1
公开(公告)日：2014-05-01
申请号：US14149339
申请日：2014-01-07
申请人： Dell Products L.P.
发明人： Stuart Berke , William Sauber
CPC分类号： G06F9/44557 , G06F11/1016 , G06F13/409 , G11C5/04 , G11C5/14 , Y02D10/14 , Y02D10/151
摘要： An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.
摘要翻译： 一种装置，包括被配置为装配到处理系统中的第一插座中的第一连接器，所述第一连接器和第一插座符合第一标准，第二插座被配置为接纳其中的存储器模块，所述第二插座和所述存储器模块符合 第二标准，通信地耦合到第一连接器和第二插座的存储缓冲器模块，所述存储器缓冲模块被配置为从所述第一连接器接收与所述第一标准相关联的信号，并将与所述第二标准相关联的信号输出到所述第二插座，以及 虚拟化模块，其通信地耦合到所述存储器缓冲器模块，所述第一连接器和所述第二插座，所述虚拟化模块被配置为从所述第二插座接收与所述第二标准相关联的第一初始化数据，并将与所述第一标准相关联的第二初始化数据输出到 处理系统。
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公开(公告)号：US20140122856A1
公开(公告)日：2014-05-01
申请号：US14149229
申请日：2014-01-07
申请人： Dell Products L.P.
发明人： Stuart Berke , William Sauber
IPC分类号： G06F9/445
CPC分类号： G06F9/44557 , G06F11/1016 , G06F13/409 , G11C5/04 , G11C5/14 , Y02D10/14 , Y02D10/151
摘要： An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.
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公开(公告)号：US20180356994A1
公开(公告)日：2018-12-13
申请号：US15620086
申请日：2017-06-12
申请人： Dell Products, L.P.
发明人： Stuart Berke , Gary Kotzur
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0619 , G06F3/0665 , G06F3/0689
摘要： A software assist module of a system memory coupled to a host processor provides the ability to offload software operations from the host processor. The software assist module includes a first memory accessed by the host processor via a first chip select signal. The software assist module also includes a software assist controller accessed by the host processor via a second chip select signal. The software assist controller is configured to intercept data related to a software function offloaded from the host processor, where the data is intercepted from a first chip select signal used to access the first memory. The software assist controller utilizes the intercepted data to perform the offloaded function. Based on configuration instructions provided by the host processor via the second chip select signal, the software assist module performs the offloaded function incrementally as function data is intercepted or as a single operation after all data for a function has been intercepted.
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公开(公告)号：US09229747B2
公开(公告)日：2016-01-05
申请号：US14149229
申请日：2014-01-07
申请人： Dell Products L.P.
发明人： Stuart Berke , William Sauber
CPC分类号： G06F9/44557 , G06F11/1016 , G06F13/409 , G11C5/04 , G11C5/14 , Y02D10/14 , Y02D10/151
摘要： An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.
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公开(公告)号：US10990291B2
公开(公告)日：2021-04-27
申请号：US15620086
申请日：2017-06-12
申请人： Dell Products, L.P.
发明人： Stuart Berke , Gary Kotzur
IPC分类号： G06F3/06 , G06F12/06 , G06F12/0873 , G06F9/38 , G06F12/0846
摘要： A software assist module of a system memory coupled to a host processor provides the ability to offload software operations from the host processor. The software assist module includes a first memory accessed by the host processor via a first chip select signal. The software assist module also includes a software assist controller accessed by the host processor via a second chip select signal. The software assist controller is configured to intercept data related to a software function offloaded from the host processor, where the data is intercepted from a first chip select signal used to access the first memory. The software assist controller utilizes the intercepted data to perform the offloaded function. Based on configuration instructions provided by the host processor via the second chip select signal, the software assist module performs the offloaded function incrementally as function data is intercepted or as a single operation after all data for a function has been intercepted.
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公开(公告)号：US09710179B2
公开(公告)日：2017-07-18
申请号：US14829314
申请日：2015-08-18
申请人： Dell Products L.P.
发明人： John Erven Jenne , Stuart Berke
CPC分类号： G06F3/0619 , G06F1/30 , G06F1/3206 , G06F3/0604 , G06F3/0647 , G06F3/0685 , G06F2212/205
摘要： In accordance with embodiments of the present disclosure, an information handling system may include a processor and a management controller communicatively coupled to the processor and configured to, during boot of the information handling system determine a first amount of energy required by the information handling system to perform a save operation to transfer data from a volatile memory to a non-volatile memory of a persistent memory in response to a loss of power for supplying electrical energy to the information handling system, determine whether a second amount of energy available for providing electrical energy for the save operation in response to the loss of power exceeds the first amount of energy, and responsive to determining whether the second amount of energy exceeds the first amount of energy, determine whether to support the persistent memory.
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公开(公告)号：US20170052716A1
公开(公告)日：2017-02-23
申请号：US14829314
申请日：2015-08-18
申请人： Dell Products L.P.
发明人： John Erven Jenne , Stuart Berke
CPC分类号： G06F3/0619 , G06F1/30 , G06F1/3206 , G06F3/0604 , G06F3/0647 , G06F3/0685 , G06F2212/205
摘要： In accordance with embodiments of the present disclosure, an information handling system may include a processor and a management controller communicatively coupled to the processor and configured to, during boot of the information handling system determine a first amount of energy required by the information handling system to perform a save operation to transfer data from a volatile memory to a non-volatile memory of a persistent memory in response to a loss of power for supplying electrical energy to the information handling system, determine whether a second amount of energy available for providing electrical energy for the save operation in response to the loss of power exceeds the first amount of energy, and responsive to determining whether the second amount of energy exceeds the first amount of energy, determine whether to support the persistent memory.
摘要翻译： 根据本公开的实施例，信息处理系统可以包括通信地耦合到处理器的处理器和管理控制器，其被配置为在信息处理系统的引导期间确定信息处理系统所需的第一能量量 响应于向信息处理系统提供电能的功率损失，执行保存操作以将数据从易失性存储器传送到永久存储器的非易失性存储器，确定是否有可用于提供电能的第二量的能量 为了响应于功率损失超过第一能量量的保存操作，并且响应于确定第二能量量是否超过第一能量量，确定是否支持持久存储器。
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