公开(公告)号：US20250138832A1

公开(公告)日：2025-05-01

申请号：US18495112

申请日：2023-10-26

Applicant: Dell Products L.P.

Inventor： Chih-Chung Chen ,  Shih-Chieh Hsu

IPC: G06F9/4401

Abstract: A multi-path initialization system includes a chassis. At least one storage device is housed in the chassis and includes an initialization path database storing respective initialization path information for each of a plurality of different initialization paths, and an initialization firmware volume database storing a plurality of initialization firmware volumes. An initialization subsystem is housed in the chassis, is coupled to the storage device(s), and receives an initialization path instruction to perform an initialization process according to an initialization path. The initialization subsystem identifies initialization path information for the initialization path that is included in the plurality of different initialization paths in the initialization path database, and identifies a subset of the plurality of initialization firmware volumes in the initialization firmware volume database based on the initialization path information. The initialization subsystem then performs the initialization process using the subset of the plurality of initialization firmware volumes.

公开(公告)号：US11663018B2

公开(公告)日：2023-05-30

申请号：US17747502

申请日：2022-05-18

Applicant: Dell Products L.P.

Inventor： Chih-Chung Chen ,  Shih-Hao Wang

IPC: G06F9/44 ,  G06F12/02 ,  G06F9/4401 ,  G06F12/126 ,  G06F13/16

CPC classification number: G06F9/4408 ,  G06F9/4411 ,  G06F12/0238 ,  G06F12/126 ,  G06F13/1689

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem. Subsequently, during second initialization operations and based on the respective unavailable memory device identifier(s) stored in the non-volatile storage subsystem, the BIOS engine generates a memory overlay that hides each unavailable memory device from the memory controller device such that the memory controller device determines that the memory system does not include any unavailable memory devices during the second initialization operations.

公开(公告)号：US11347520B2

公开(公告)日：2022-05-31

申请号：US16789994

申请日：2020-02-13

Applicant: Dell Products L.P.

Inventor： Chih-Chung Chen ,  Shih-Hao Wang

IPC: G06F9/44 ,  G06F9/4401 ,  G06F12/126 ,  G06F12/02 ,  G06F13/16

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem. Subsequently, during second initialization operations and based on the respective unavailable memory device identifier(s) stored in the non-volatile storage subsystem, the BIOS engine generates a memory overlay that hides each unavailable memory device from the memory controller device such that the memory controller device determines that the memory system does not include any unavailable memory devices during the second initialization operations.

公开(公告)号：US11023024B1

公开(公告)日：2021-06-01

申请号：US16781687

申请日：2020-02-04

Applicant: Dell Products L.P.

Inventor： Chih-Chung Chen ,  Feng-Yu Wu ,  Gin-Yen Yang

IPC: G06F1/26 ,  G06F9/4401 ,  G06F13/42 ,  G06F13/20

Abstract: A voltage regulator configuration system includes a voltage regulator module that is coupled to a processing system and that is configured to provide a voltage to the processing system. A Basic Input/Output System (BIOS) that is also coupled to the processing system and the BIOS identifies a processing system mode in which the processing system is operating and identifies a voltage regulator module configuration for the voltage regulator module based on the processing system mode. The BIOS transmits a voltage regulator module configuration command that includes the voltage regulator module configuration to a remote access controller. The remote access controller configures the voltage regulator module with the voltage regulator module configuration.

公开(公告)号：US20220276873A1

公开(公告)日：2022-09-01

申请号：US17747502

申请日：2022-05-18

Applicant: Dell Products L.P.

Inventor： Chih-Chung Chen ,  Shih-Hao Wang

IPC: G06F9/4401 ,  G06F12/126 ,  G06F12/02 ,  G06F13/16

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem. Subsequently, during second initialization operations and based on the respective unavailable memory device identifier(s) stored in the non-volatile storage subsystem, the BIOS engine generates a memory overlay that hides each unavailable memory device from the memory controller device such that the memory controller device determines that the memory system does not include any unavailable memory devices during the second initialization operations.