公开(公告)号：US20230325569A1

公开(公告)日：2023-10-12

申请号：US17716527

申请日：2022-04-08

Applicant: Dell Products L.P.

Inventor： Vijender Kumar ,  Mallikarjun Vasa ,  Ashish Shrivastava ,  Bhyrav Mutnury ,  Seema P K ,  Sukumar Muthusamy ,  Sanjay Kumar ,  Sunil Pathania

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F2119/08

Abstract: An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.

公开(公告)号：US20250048549A1

公开(公告)日：2025-02-06

申请号：US18363106

申请日：2023-08-01

Applicant: DELL PRODUCTS L.P.

Inventor： Sanjay Kumar ,  Sathvika Bandi ,  Sukumar Muthusamy ,  Naga Hara Sathya Sree Tammisetti ,  Arun Vignesh Palanichamy ,  Bhyrav Mutnury

IPC: H05K1/03 ,  H05K1/02

Abstract: A printed circuit board substrate including multiple sets of glass rows. The multiple sets of glass rows include a first set of glass rows, a second set of glass rows, and a third set of glass rows. The first set of glass rows extend in a first direction. The second set of glass rows extend in a second direction that is perpendicular to the first direction. The third set of glass rows extend in a third direction that is parallel to the first direction. The resin holds the multiple sets of glass rows together and to fill pockets between the multiple of sets of glass rows.

公开(公告)号：US11831477B2

公开(公告)日：2023-11-28

申请号：US17712775

申请日：2022-04-04

Applicant: Dell Products L.P.

Inventor： Vijender Kumar ,  Douglas Wallace ,  Bhyrav Mutnury ,  Sukumar Muthusamy

IPC: H04B1/16 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/03063

Abstract: An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface. The second component receives the training runs, provides for each training run a set of tap settings for each tap input, determines whether or not a variation in the tap settings for the training runs is greater than a predetermined variation value, and, when the variation is greater than the predetermined variation value, sets the first input to configure the first equalization stage from the first low equalization state to the first high equalization state.

公开(公告)号：US20230318886A1

公开(公告)日：2023-10-05

申请号：US17712775

申请日：2022-04-04

Applicant: Dell Products L.P.

Inventor： Vijender Kumar ,  Douglas Wallace ,  Bhyrav Mutnury ,  Sukumar Muthusamy

IPC: H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/03063

Abstract: An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface. The second component receives the training runs, provides for each training run a set of tap settings for each tap input, determines whether or not a variation in the tap settings for the training runs is greater than a predetermined variation value, and, when the variation is greater than the predetermined variation value, sets the first input to configure the first equalization stage from the first low equalization state to the first high equalization state.