公开(公告)号：US12238855B2

公开(公告)日：2025-02-25

申请号：US17510542

申请日：2021-10-26

Applicant: Dell Products L.P.

Inventor： Vijender Kumar ,  Malikarjun Vasa ,  Bhyrav Mutnury

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: A printed circuit board (PCB) includes first and second signal pads and a guard trace formed on a surface of the PCB. The first and second signal pads are for connecting to signal contacts of a high-speed data communication interface. The guard trace is located between the first signal pad and the second signal pad. The PCB further includes first, second, and third ground vias that couple the guard trace to a ground plane of the PCB. The first ground via is located at a first end of the guard trace. The second ground via is located at a second end of the guard trace. The third ground via is located between the first via and the second via.

公开(公告)号：US11831477B2

公开(公告)日：2023-11-28

申请号：US17712775

申请日：2022-04-04

Applicant: Dell Products L.P.

Inventor： Vijender Kumar ,  Douglas Wallace ,  Bhyrav Mutnury ,  Sukumar Muthusamy

IPC: H04B1/16 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/03063

Abstract: An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface. The second component receives the training runs, provides for each training run a set of tap settings for each tap input, determines whether or not a variation in the tap settings for the training runs is greater than a predetermined variation value, and, when the variation is greater than the predetermined variation value, sets the first input to configure the first equalization stage from the first low equalization state to the first high equalization state.

公开(公告)号：US20230318886A1

公开(公告)日：2023-10-05

申请号：US17712775

申请日：2022-04-04

Applicant: Dell Products L.P.

Inventor： Vijender Kumar ,  Douglas Wallace ,  Bhyrav Mutnury ,  Sukumar Muthusamy

IPC: H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/03063

Abstract: An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface. The second component receives the training runs, provides for each training run a set of tap settings for each tap input, determines whether or not a variation in the tap settings for the training runs is greater than a predetermined variation value, and, when the variation is greater than the predetermined variation value, sets the first input to configure the first equalization stage from the first low equalization state to the first high equalization state.

公开(公告)号：US20250045058A1

公开(公告)日：2025-02-06

申请号：US18460260

申请日：2023-09-01

Applicant: DELL PRODUCTS L.P.

Inventor： Douglas S. Winterberg ,  Vijender Kumar ,  Bhyrav Mutnury

IPC: G06F9/4401

Abstract: An information handling system includes a baseboard management controller (BMC), an I/O device, and a BIOS. The BIOS initializes a parameter of the I/O device with a particular value, and includes an I/O health check module. Each time the BIOS initializes the first parameter, the I/O health check module receives the particular value, determines whether or not the particular value is within a predetermined range of values, and provides the particular value to the BMC. The BMC logs the values from each time the BIOS initializes the parameter, determines a health status for the information handling system based upon the logged values, and provides an indication of the health status.

公开(公告)号：US20230325569A1

公开(公告)日：2023-10-12

申请号：US17716527

申请日：2022-04-08

Applicant: Dell Products L.P.

Inventor： Vijender Kumar ,  Mallikarjun Vasa ,  Ashish Shrivastava ,  Bhyrav Mutnury ,  Seema P K ,  Sukumar Muthusamy ,  Sanjay Kumar ,  Sunil Pathania

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F2119/08

Abstract: An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.

公开(公告)号：US20230030534A1

公开(公告)日：2023-02-02

申请号：US17510542

申请日：2021-10-26

Applicant: Dell Products L.P.

Inventor： Vijender Kumar ,  Malikarjun Vasa ,  Bhyrav Mutnury

IPC: H05K1/02

Abstract: A printed circuit board (PCB) includes first and second signal voids and a guard trace formed on a surface of the PCB. The first and second signal voids are for connecting to signal contacts of a high-speed data communication interface. The guard trace is located between the first signal void and the second signal void. The PCB further includes first, second, and third ground vias that couple the guard trace to a ground plane of the PCB. The first ground via is located at a first end of the guard trace. The second ground via is located at a second end of the guard trace. The third ground via is located between the first via and the second via.