公开(公告)号：US07085149B2

公开(公告)日：2006-08-01

申请号：US10764000

申请日：2004-01-23

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Ross Alan Kohler ,  Richard Joseph McPartland ,  Hai Quang Pham

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Ross Alan Kohler ,  Richard Joseph McPartland ,  Hai Quang Pham

IPC分类号： G11C17/08

CPC分类号： G11C17/12 ,  G11C7/12

摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by applying a biased gate voltage (relative to a source voltage) to the gate of at least one of transistor in the array. The biased gate voltage is applied at least during a precharge phase of a read cycle. When the array transistors are n-channel transistors, the biased voltage is a negative bias voltage (relative to the source voltage). When the array transistors are p-channel transistors, the biased voltage is a positive bias voltage (relative to the source voltage). Applying a negative backgate bias to the transistor's p-well contact can also reduce n-channel transistor subthreshold leakage current. Thus, for an n-channel array, a negative gate voltage and backgate bias (optional) are applied to cell transistors in the off state. Similarly, the subthreshold leakage current of p-channel transistors is reduced by applying a more positive gate-to-source bias and a positive n-well-to-source bias.

摘要翻译： 提供了一种用于减少只读存储器件中的漏电流的方法和装置。 通过将偏置的栅极电压（相对于源极电压）施加到阵列中的至少一个晶体管的栅极来降低泄漏电流。 至少在读周期的预充电阶段期间施加偏置栅极电压。 当阵列晶体管是n沟道晶体管时，偏置电压是负偏置电压（相对于源极电压）。 当阵列晶体管是p沟道晶体管时，偏置电压是正偏置电压（相对于源极电压）。 对晶体管的p阱接触施加负的背栅极偏置还可以减少n沟道晶体管的亚阈值漏电流。 因此，对于n沟道阵列，负栅极电压和背栅极偏置（可选）被施加到处于断开状态的单元晶体管。 类似地，p沟道晶体管的亚阈值漏电流通过施加更正的栅极至源极偏压和正的n阱到源偏压来减小。

公开(公告)号：US07460424B2

公开(公告)日：2008-12-02

申请号：US11619344

申请日：2007-01-03

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Richard Joseph McPartland ,  Hai Quang Pham

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Richard Joseph McPartland ,  Hai Quang Pham

IPC分类号： G11C17/12

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.

摘要翻译： 提供了一种用于减少只读存储器件中的漏电流的方法和装置。 通过在每个读取周期期间减少预充电周期的持续时间来降低泄漏电流，使得相关联的泄漏电流将在每个周期期间流动更短的时间段。 预充电阶段位于每个读取周期的开始之前，在评估阶段之前。 预充电阶段由后续时钟边沿或后续时钟边沿之前的内部超时终止。 列达到其预充电电压和评估阶段开始之间的时间间隔减小。

公开(公告)号：US07177212B2

公开(公告)日：2007-02-13

申请号：US10764150

申请日：2004-01-23

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Richard Joseph McPartland ,  Hai Quang Pham

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Richard Joseph McPartland ,  Hai Quang Pham

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.

摘要翻译： 提供了一种用于减少只读存储器件中的漏电流的方法和装置。 通过在每个读取周期期间减少预充电周期的持续时间来降低泄漏电流，使得相关联的泄漏电流将在每个周期期间流动更短的时间段。 预充电阶段位于每个读取周期的开始之前，在评估阶段之前。 预充电阶段由后续时钟边沿或后续时钟边沿之前的内部超时终止。 列达到其预充电电压和评估阶段开始之间的时间间隔减小。

公开(公告)号：US07042779B2

公开(公告)日：2006-05-09

申请号：US10764152

申请日：2004-01-23

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Richard Joseph McPartland ,  Hai Quang Pham

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Richard Joseph McPartland ,  Hai Quang Pham

IPC分类号： G11C7/00

CPC分类号： G11C17/12 ,  G11C7/12

摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharged is limited to a subset of columns that includes those columns that will be read during a given read cycle. A read column address is decoded to precharge only the portion of the columns of transistors that will be read during the given read cycle. The columns of transistors can be grouped into a plurality of sub-arrays and only those sub-arrays having columns that will be read during a given read cycle are precharged during the read cycle.

摘要翻译： 提供了一种用于减少只读存储器件中的漏电流的方法和装置。 在给定的读取周期期间，通过在只读存储器阵列中只预先充电一部分列来减少泄漏电流。 预充电的列的部分被限制为包括在给定读周期期间将被读取的列的列的子集。 对读取列地址进行解码，以仅对在给定读取周期期间将被读取的晶体管列的部分进行预充电。 晶体管的列可以被分组成多个子阵列，并且仅在具有在给定读周期期间被读取的列的那些子阵列在读周期期间被预充电。

公开(公告)号：US08365044B2

公开(公告)日：2013-01-29

申请号：US11738827

申请日：2007-04-23

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

IPC分类号： G11C29/00

CPC分类号： G11C29/846 ,  G11C17/14

摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.

摘要翻译： 存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。 错误校正电路被配置为在从存储器阵列检索的数据字中识别与存储器阵列中的预定缺陷位置相对应的至少一个位位置，并且通过自动反转在该存储器阵列中的逻辑值来产生校正数据字 识别位位置。 这种自动逻辑反转方法特别适用于校正与高密度ROM器件中的通孔缺陷和弱位缺陷相关联的输出数据错误。

公开(公告)号：US07391633B2

公开(公告)日：2008-06-24

申请号：US11460045

申请日：2006-07-26

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C7/067

摘要： A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.

摘要翻译： 与包括多个匹配线的CAM电路一起使用的感测电路和连接到匹配线的多个CAM单元包括至少一个电荷共享电路和连接到电荷共享电路的至少一个开关电路。 开关电路用于根据提供给开关电路的第一控制信号选择性地将电荷共享电路连接到匹配线中的对应的一个。 感测电路还包括连接到对应匹配线的至少一个比较器电路，用于产生指示提供给连接到相应匹配线的至少一个给定的一个CAM单元的搜索数据和存储的数据之间的匹配的输出信号 在给定的CAM单元格中。 电荷共享电路用于去除相应匹配线上的电荷量，以便结合CAM单元的搜索操作来减小相应匹配线上的电压。

公开(公告)号：US20080025103A1

公开(公告)日：2008-01-31

申请号：US11460035

申请日：2006-07-26

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

IPC分类号： G11C11/34

CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C7/12

摘要： A single-ended sensing circuit is provided for use with a memory circuit including a plurality of bit lines and a plurality of memory cells connected to the bit lines. The sensing circuit includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to at least a given one of the bit lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the given bit line. The comparator circuit is operative to generate an output signal indicative of a logical state of a memory cell connected to the given bit line. The charge sharing circuit is operative to remove an amount of charge on the given bit line so as to reduce a voltage on the given bit line in conjunction with a read access of the memory cell.

摘要翻译： 提供单端感测电路用于与包括多个位线的多个存储器单元连接的存储器电路和与位线连接的多个存储器单元。 感测电路包括至少一个电荷共享电路和连接到电荷共享电路的至少一个开关电路。 开关电路用于根据提供给开关电路的第一控制信号选择性地将电荷共享电路连接到位线中的至少一个给定的位线。 感测电路还包括连接到给定位线的至少一个比较器电路。 比较器电路用于产生指示连接到给定位线的存储器单元的逻辑状态的输出信号。 电荷共享电路用于去除给定位线上的电荷量，以便结合存储器单元的读取访问来减小给定位线上的电压。

公开(公告)号：US07848172B2

公开(公告)日：2010-12-07

申请号：US12276576

申请日：2008-11-24

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C8/12

摘要： A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.

摘要翻译： 具有降低的功耗的存储器电路包括多个存储器子阵列和耦合到每个存储器子阵列的共享电路。 每个存储器子阵列包括至少一个行电路，至少一个列电路和可操作地耦合到行和列电路的多个存储单元。 行和列电路可操作以提供对一个或多个存储器单元的选择性访问。 共享电路包括存储器子阵列外部的电路，其可操作以根据提供给存储器电路的至少一个控制信号来控制存储器子阵列的一个或多个功能。 存储器电路是可操作的，其中存储器子阵列中的至少一个可操作，其中一个或多个存储器子阵列供电并与未被供电的一个或多个存储器子阵列同时发送。

公开(公告)号：US20100246293A1

公开(公告)日：2010-09-30

申请号：US12415248

申请日：2009-03-31

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

IPC分类号： G11C7/00

CPC分类号： G11C7/04 ,  G11C7/12 ,  G11C7/22

摘要： A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.

摘要翻译： 存储器电路包括多个存储单元和连接到存储器单元的多个位线和行线，用于访问所选存储单元。 存储器电路包括可编程电压源，其适于连接到至少一个位线，并且可操作以在访问耦合到位线的存储器单元中的所选择的一个之前将位线预充电至规定的电压电平。 耦合到位线的控制电路在给定存储器读取周期的至少一部分期间可操作地与位线的放电相对抗。 连接到控制电路的跟踪电路用于控制控制电路的启动延迟和/或控制电路有效的持续时间作为影响位线上的数据信号的信号展开时间的参数的函数 。

公开(公告)号：US20100220534A1

公开(公告)日：2010-09-02

申请号：US12161818

申请日：2007-08-13

申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

IPC分类号： G11C7/10 ,  G11C5/14 ,  G11C29/12

CPC分类号： G11C29/12 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/06 ,  G11C29/1201 ,  G11C2207/2227

摘要： A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.

摘要翻译： 存储器件包括存储器阵列，耦合到存储器阵列的至少一个缓冲器以及耦合到缓冲器的测试电路。 缓冲器包括被配置为至少部分地基于由测试电路产生的控制信号将缓冲器的第一和第二输入复用到缓冲器的给定输出的开关电路。 根据指示存储器件的测试操作模式的测试信号和表示存储器件的掉电操作模式的掉电信号，产生控制信号。 缓冲器还包括响应于控制信号的电流降低电路，用于减少在掉电操作模式下由缓冲器消耗的电流量。 缓冲器可以包括存储器件的输入数据缓冲器或地址缓冲器。