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公开(公告)号：US20080217658A1
公开(公告)日：2008-09-11
申请号：US11683075
申请日：2007-03-07
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.
摘要翻译： 本发明提供了利用电迁移进行编程的反熔丝的结构。 通过在没有导电材料的情况下提供具有高电阻的一部分反熔丝连接，然后通过将导电材料电迁移到反熔丝连接中，反熔丝结构的电阻改变。 通过在反熔丝链路上设置端子，检测和感测反熔丝连接的电特性的变化。 还公开了具有内置感测装置的集成反熔丝和可共享编程晶体管和感测电路的集成反熔丝的二维阵列。
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公开(公告)号：US07714326B2
公开(公告)日：2010-05-11
申请号：US11683075
申请日：2007-03-07
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.
摘要翻译： 本发明提供了利用电迁移进行编程的反熔丝的结构。 通过在没有导电材料的情况下提供具有高电阻的一部分反熔丝连接，然后通过将导电材料电迁移到反熔丝连接中，反熔丝结构的电阻改变。 通过在反熔丝链路上设置端子，检测和感测反熔丝连接的电特性的变化。 还公开了具有内置感测装置的集成反熔丝和可共享编程晶体管和感测电路的集成反熔丝的二维阵列。
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公开(公告)号：US08004060B2
公开(公告)日：2011-08-23
申请号：US11946938
申请日：2007-11-29
申请人： Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Norman W. Robson , John M. Safran , Kenneth J. Stein
发明人： Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Norman W. Robson , John M. Safran , Kenneth J. Stein
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.
摘要翻译： 金属层和半导体层顺序地沉积在基板上。 半导体层和金属层被光刻图案化以形成半导体部分和金属栅极部分的堆叠，其优选地与至少一个金属栅极叠层的形成同时进行。 在一个实施例中，半导体部分的尺寸减小，并且金属半导体合金部分通过金属化形成在半导体部分上。 在由此形成的第一电反熔丝中，金属半导体合金部分可以电铸以在金属半导体合金部分和金属栅极部分之间形成短路。 在另一个实施例中，在半导体部分上形成两个非接合的金属半导体合金部分。 在由此形成的第二电反熔丝中，金属半导体合金部分可以被电铸以在两个先前接合的金属半导体合金部分之间形成短路。
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公开(公告)号：US20090141533A1
公开(公告)日：2009-06-04
申请号：US11946938
申请日：2007-11-29
申请人： Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Norman W. Robson , John M. Safran , Kenneth J. Stein
发明人： Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Norman W. Robson , John M. Safran , Kenneth J. Stein
IPC分类号： G11C17/08 , H01L27/20 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.
摘要翻译： 金属层和半导体层顺序地沉积在基板上。 半导体层和金属层被光刻图案化以形成半导体部分和金属栅极部分的堆叠，其优选地与至少一个金属栅极叠层的形成同时进行。 在一个实施例中，半导体部分的尺寸减小，并且金属半导体合金部分通过金属化形成在半导体部分上。 在由此形成的第一电反熔丝中，金属半导体合金部分可以电铸以在金属半导体合金部分和金属栅极部分之间形成短路。 在另一个实施例中，在半导体部分上形成两个非接合的金属半导体合金部分。 在由此形成的第二电反熔丝中，金属半导体合金部分可以被电铸以在两个先前接合的金属半导体合金部分之间形成短路。
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公开(公告)号：US20080157125A1
公开(公告)日：2008-07-03
申请号：US11616965
申请日：2006-12-28
申请人： Deok-kee Kim , Byeongju Park , John M. Safran
发明人： Deok-kee Kim , Byeongju Park , John M. Safran
IPC分类号： H01L27/105 , H01L29/423
CPC分类号： H01L23/5252 , G11C17/16 , G11C17/18 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.
摘要翻译： 本发明提供了一种集成反熔丝的结构，该结构集成了具有集成加热器的集成感测晶体管。 连接到上板的两个端子允许上板的加热，加速在更低偏压下的反熔丝电介质的击穿。 上板的一部分也用作集成感测晶体管的栅极。 反熔丝电介质用作集成晶体管的栅极电介质。 下板包括晶体管的沟道，漏极和源极。 虽然完整，集成感测晶体管允许晶体管电流通过漏极。 当编程时，作为集成晶体管的栅极的反熔丝电介质受到栅极击穿，使栅极短路到沟道并导致漏极电流降低。 集成的反熔丝结构也可以以阵列布线，以提供紧凑的OTP存储器阵列。
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公开(公告)号：US07723820B2
公开(公告)日：2010-05-25
申请号：US11616965
申请日：2006-12-28
申请人： Deok-kee Kim , Byeongju Park , John M. Safran
发明人： Deok-kee Kim , Byeongju Park , John M. Safran
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , G11C17/16 , G11C17/18 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.
摘要翻译： 本发明提供了一种集成反熔丝的结构，该结构集成了具有集成加热器的集成感测晶体管。 连接到上板的两个端子允许上板的加热，加速在更低偏压下的反熔丝电介质的击穿。 上板的一部分也用作集成感测晶体管的栅极。 反熔丝电介质用作集成晶体管的栅极电介质。 下板包括晶体管的沟道，漏极和源极。 虽然完整，集成感测晶体管允许晶体管电流通过漏极。 当编程时，作为集成晶体管的栅极的反熔丝电介质受到栅极击穿，使栅极短路到沟道并导致漏极电流降低。 集成的反熔丝结构也可以以阵列布线，以提供紧凑的OTP存储器阵列。
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7.发明授权公开(公告)号：US07345904B1
公开(公告)日：2008-03-18
申请号：US11548477
申请日：2006-10-11
申请人： Byeongju Park , Deok-Kee Kim , John M. Safran
发明人： Byeongju Park , Deok-Kee Kim , John M. Safran
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. The fuse link has a nominal maximum programming current and corresponding combinations of a programming voltage and a gate voltage associated with the nominal maximum programming current. A first programming current pulse is generated to provide a programming current less than the maximum programming current. The first programming current pulse causes electromigration to increase the resistance of the fuse link. A subsequent programming current pulse is applied using a combination of gate voltage and programming voltages which if applied to the fuse link absent any electromigration would result in a programming current greater than the nominal maximum programming current. However, the resistance created by the first programming pulse reduces the programming current of the subsequent programming pulse to a level below the maximum programming current.
摘要翻译： 用于编程电子可编程半导体熔丝的方法将编程电流作为一系列多个脉冲施加到熔丝链路。 熔丝链路具有标称最大编程电流以及与标称最大编程电流相关联的编程电压和栅极电压的对应组合。 产生第一编程电流脉冲以提供小于最大编程电流的编程电流。 第一个编程电流脉冲导致电迁移以增加熔断体的电阻。 使用栅极电压和编程电压的组合来施加随后的编程电流脉冲，如果施加到熔丝链而没有任何电迁移将导致编程电流大于标称最大编程电流。 然而，由第一编程脉冲产生的电阻将后续编程脉冲的编程电流降低到低于最大编程电流的电平。
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8.发明授权Electrically programmable fuse using anisometric contacts and fabrication method 有权电子可编程保险丝采用不规则接触和制造方法公开(公告)号：US08629049B2
公开(公告)日：2014-01-14
申请号：US13420724
申请日：2012-03-15
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.
摘要翻译： 制造电可编程熔丝法的制造方法包括在衬底上沉积多晶硅层，图案化阳极接触区域，阴极接触区域和将阴极接触区域与阳极接触区域导电连接的熔断体，其可通过应用 编程电流，在多晶硅层上沉积硅化物层，以及在预定构型中分别在阴极接触区域和阳极接触区域的硅化物层上形成多个不规则接触。
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9.发明申请SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING 失效通过局部扩散加热实现低电压编程的安全保险丝公开(公告)号：US20130063202A1
公开(公告)日：2013-03-14
申请号：US13612938
申请日：2012-09-13
IPC分类号： H01L23/544 , H01H37/76
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.
摘要翻译： 反熔丝具有一个导电类型的第一和第二半导体区域和它们之间具有相反导电类型的第三半导体区域。 接触第一区域的导电区域在横向于栅极的长尺寸方向的第二方向上具有长尺寸。 反熔丝阳极在第二方向上与第一区域间隔开，并且触点与第二区域连接。 在阳极和接触之间施加编程电压，栅极偏压足以完全导通反熔丝的场效应晶体管操作加热第一区域以向外驱动掺杂剂，导致第一区域的边缘更接近于 并且将第一和第二区域之间的电阻降低一个或多个数量级。
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10.发明授权Electrically programmable fuse using anisometric contacts and fabrication method 有权电子可编程保险丝采用不规则接触和制造方法公开(公告)号：US08519507B2
公开(公告)日：2013-08-27
申请号：US12493616
申请日：2009-06-29
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.
摘要翻译： 包括阳极接触区域和阴极接触区域的电可编程熔丝由其上形成有硅化物层的多晶硅层和导电连接阴极接触区域与阳极接触区域的熔丝链形成，该熔丝链可通过应用 编程电流，以及分别形成在阴极接触区域的硅化物层上或在阴极接触区域和阳极接触区域的硅化物层上以预定构造形成的多个不规则接触。
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