公开(公告)号：US20090096060A1

公开(公告)日：2009-04-16

申请号：US12216094

申请日：2008-06-30

申请人： Deok-kee Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  I-hun Song ,  Won-joo Kim ,  Young-gu Jin ,  Hyuk-soon Choi ,  Suk-pil Kim

发明人： Deok-kee Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  I-hun Song ,  Won-joo Kim ,  Young-gu Jin ,  Hyuk-soon Choi ,  Suk-pil Kim

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.

摘要翻译： 提供了防泡结构，反熔丝阵列，制造方法和操作方法。 反熔丝结构包括在半导体衬底内形成为第一扩散区的位线，形成在位线上的绝缘层，以及形成在绝缘层上的字线。 反熔丝阵列包括排列成阵列的多个反熔丝结构。

公开(公告)号：US08058701B2

公开(公告)日：2011-11-15

申请号：US12216094

申请日：2008-06-30

申请人： Deok-kee Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  I-hun Song ,  Won-joo Kim ,  Young-gu Jin ,  Hyuk-soon Choi ,  Suk-pil Kim

发明人： Deok-kee Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  I-hun Song ,  Won-joo Kim ,  Young-gu Jin ,  Hyuk-soon Choi ,  Suk-pil Kim

IPC分类号： H01L23/52

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.

摘要翻译： 提供了防泡结构，反熔丝阵列，制造方法和操作方法。 反熔丝结构包括在半导体衬底内形成为第一扩散区的位线，形成在位线上的绝缘层，以及形成在绝缘层上的字线。 反熔丝阵列包括排列成阵列的多个反熔丝结构。

公开(公告)号：US20090206978A1

公开(公告)日：2009-08-20

申请号：US12379347

申请日：2009-02-19

申请人： Soo-Jung Hwang ,  Deok-kee Kim ,  Jung-hun Sung ,  I-hun Song ,  Hyuk-soon Choi

发明人： Soo-Jung Hwang ,  Deok-kee Kim ,  Jung-hun Sung ,  I-hun Song ,  Hyuk-soon Choi

IPC分类号： H01H85/10

CPC分类号： G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Example embodiments relate to an electrical device, for example, to an electrical fuse device that includes a fuse link for linking a cathode and anode. An electrical device may include a cathode, an anode, and a fuse link. The fuse link may link the cathode and the anode. The fuse link may include a multi-metal layer structure. The fuse link may include a first metal layer including a first resistance, and a second metal layer stacked on the first metal layer and including a second resistance. The first resistance may be different from the second resistance. The fuse link may include a weak point as a region at which electrical blowing is performed easier than other regions of the fuse link.

摘要翻译： 示例性实施例涉及电气设备，例如电气熔断器件，其包括用于连接阴极和阳极的熔断体。 电气设备可以包括阴极，阳极和熔断体。 熔丝链可以连接阴极和阳极。 熔丝链可以包括多金属层结构。 熔丝连接件可以包括第一金属层和第二金属层，第一金属层包括第一电阻，第二金属层堆叠在第一金属层上并包括第二电阻。 第一阻力可能与第二阻力不同。 熔断体可以包括作为进行电吹送的区域的弱点比熔丝链的其它区域更容易。

公开(公告)号：US20060286461A1

公开(公告)日：2006-12-21

申请号：US11448113

申请日：2006-06-07

申请人： Kwang-hee Kim ,  Chang-hoon Jung ,  Young-gu Jin ,  Byong-ho Cheong ,  Hyuk-soon Choi

发明人： Kwang-hee Kim ,  Chang-hoon Jung ,  Young-gu Jin ,  Byong-ho Cheong ,  Hyuk-soon Choi

IPC分类号： G03F1/00

CPC分类号： G02B3/0012 ,  G02B3/0056

摘要： A micro lens array and method of fabricating the micro lens array. The micro lens array includes: a substrate; a plurality of holes penetrating the substrate; and a plurality of lens units on a first surface of the substrate, each lens being at a respective one of the plurality of holes. When the micro lens array is applied to a display device, a high contrast ratio can be obtained, and the light can be transmitted in a single direction.

公开(公告)号：US07580190B2

公开(公告)日：2009-08-25

申请号：US11448113

申请日：2006-06-07

申请人： Kwang-hee Kim ,  Chang-hoon Jung ,  Young-gu Jin ,  Byong-ho Cheong ,  Hyuk-soon Choi

发明人： Kwang-hee Kim ,  Chang-hoon Jung ,  Young-gu Jin ,  Byong-ho Cheong ,  Hyuk-soon Choi

IPC分类号： G02B27/10 ,  B05D5/06

CPC分类号： G02B3/0012 ,  G02B3/0056

摘要： A micro lens array and method of fabricating the micro lens array. The micro lens array includes: a substrate; a plurality of holes penetrating the substrate; and a plurality of lens units on a first surface of the substrate, each lens being at a respective one of the plurality of holes. When the micro lens array is applied to a display device, a high contrast ratio can be obtained, and the light can be transmitted in a single direction.

摘要翻译： 微透镜阵列及其制造方法。 微透镜阵列包括：基板; 贯穿基板的多个孔; 以及在所述基板的第一表面上的多个透镜单元，每个透镜位于所述多个孔中的相应一个孔中。 当将微透镜阵列施加到显示装置时，可以获得高对比度，并且可以沿单个方向透射光。

公开(公告)号：US08835985B2

公开(公告)日：2014-09-16

申请号：US13208671

申请日：2011-08-12

申请人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

发明人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

IPC分类号： H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/408 ,  H01L29/66462

摘要： According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant.

摘要翻译： 根据示例性实施例，功率电子器件包括第一半导体层，第一半导体层的第一表面上的第二半导体层以及第二半导体层上的源极，漏极和栅极。 源极，漏极和栅极彼此分开。 电力电子设备还包括在第一半导体层和第二半导体层之间的界面处的二维电子气体（2DEG）区域，栅极上的第一绝缘层和与第一绝缘层相邻的第二绝缘层。 第一绝缘层具有第一介电常数，第二绝缘层具有小于第一介电常数的第二介电常数。

公开(公告)号：US08790998B2

公开(公告)日：2014-07-29

申请号：US12588828

申请日：2009-10-29

申请人： Ki-ha Hong ,  Kyoung-won Park ,  Jai-kwang Shin ,  Jong-seob Kim ,  Hyuk-soon Choi

发明人： Ki-ha Hong ,  Kyoung-won Park ,  Jai-kwang Shin ,  Jong-seob Kim ,  Hyuk-soon Choi

IPC分类号： H01L21/302 ,  H01L21/336 ,  H01L21/84 ,  H01L21/20 ,  H01L29/12 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/125 ,  B82Y10/00 ,  H01L29/127 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696 ,  Y10T156/10 ,  Y10T156/1082

摘要： Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.

摘要翻译： 示例性实施例涉及形成核 - 壳结构的方法。 根据一种方法，在基板上限定形成芯 - 壳结构的区域，并且可以在限定区域中顺序堆叠芯层和壳层。 第一壳层可以进一步形成在衬底和芯之间。 当核心层和壳层依次层叠在芯 - 壳区域中时，该方法还可以包括在基板上形成凹槽，形成覆盖凹槽表面的第一壳层，在其表面的凹槽中形成芯 被第一壳层覆盖，并且形成覆盖芯的第二壳层。

公开(公告)号：US08569769B2

公开(公告)日：2013-10-29

申请号：US13179859

申请日：2011-07-11

申请人： In-jun Hwang ,  Ki-ha Hong ,  Jong-seob Kim ,  Jae-Kwang Shin ,  Jae-joon Oh ,  Jong-bong Ha ,  Hyuk-soon Choi

发明人： In-jun Hwang ,  Ki-ha Hong ,  Jong-seob Kim ,  Jae-Kwang Shin ,  Jae-joon Oh ,  Jong-bong Ha ,  Hyuk-soon Choi

IPC分类号： H01L29/15

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess.

摘要翻译： 增强模式（E模式）高电子迁移率晶体管（HEMT）包括具有二维电子气体（2DEG）的沟道层，在沟道层中引起2DEG的势垒层，势垒层上的源极和漏极 ，源极和漏极之间的阻挡层上的耗尽层，以及耗尽层上的栅电极。 阻挡层凹陷在栅电极下方，耗尽层覆盖凹槽的表面并且延伸到围绕凹槽的阻挡层上。

公开(公告)号：US08508194B2

公开(公告)日：2013-08-13

申请号：US12923857

申请日：2010-10-12

申请人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

发明人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

IPC分类号： G05F1/10

CPC分类号： H03K17/6871 ,  H02M1/08 ,  H02M3/158 ,  H02M3/337 ,  H02M2001/0074 ,  H03K2217/0081

摘要： Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage.

摘要翻译： 提供一种半导体器件，其可以包括具有负阈值电压的开关器件，以及电源端子和接地端子之间的驱动单元，并且提供用于驱动开关器件的驱动电压。 开关器件可以连接到具有大于从接地端子提供的接地电压的虚拟接地电压的虚拟接地节点，并且当驱动电压和虚拟接地电压之间的差大于负值时，可以导通 阈值电压。

公开(公告)号：US20130032816A1

公开(公告)日：2013-02-07

申请号：US13431397

申请日：2012-03-27

申请人： In-jun Hwang ,  Hyuk-soon Choi ,  Jae-joon Oh ,  Jong-bong Ha ,  Jong-seob Kim ,  Ki-ha Hong ,  Jai-kwang Shin

发明人： In-jun Hwang ,  Hyuk-soon Choi ,  Jae-joon Oh ,  Jong-bong Ha ,  Jong-seob Kim ,  Ki-ha Hong ,  Jai-kwang Shin

IPC分类号： H01L29/20 ,  H01L21/335 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/7787

摘要： High electron mobility transistors (HEMTs) including a substrate and a HEMT stack on the substrate, the HEMT stack including a compound semiconductor layer that includes a 2-dimensional electron gas (2DEG), an upper compound semiconductor layer that has a polarization index higher than a polarization index of the compound semiconductor layer, and a source electrode, a drain electrode, and a gate that are disposed on the upper compound semiconductor layer. The substrate may be a nitride substrate that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of a silicon substrate. The substrate may include an insulating layer that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of the silicon substrate, a metal layer that is deposited on the insulating layer, and a plate that is attached to the metal layer.