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公开(公告)号：US20090285010A1
公开(公告)日：2009-11-19
申请号：US12253735
申请日：2008-10-17
CPC分类号： G11C11/413
摘要： A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.
摘要翻译： 存储器电路包括存储器阵列，其还包括以行和列排列的多个存储单元; 多个第一位线，每个第一位线连接到存储器阵列的一列; 以及多个写入辅助锁存器，每个写入辅助锁存器连接到多个第一位线之一。 多个写入辅助锁存器中的每一个被配置为增加多个第一位线中的一个连接上的电压。
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公开(公告)号：US07898875B2
公开(公告)日：2011-03-01
申请号：US12253735
申请日：2008-10-17
IPC分类号： G11C7/10
CPC分类号： G11C11/413
摘要： A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.
摘要翻译： 存储器电路包括存储器阵列，其还包括以行和列排列的多个存储单元; 多个第一位线，每个第一位线连接到存储器阵列的一列; 以及多个写入辅助锁存器，每个写入辅助锁存器连接到多个第一位线之一。 多个写入辅助锁存器中的每一个被配置为增加多个第一位线中的一个连接上的电压。
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公开(公告)号：US08300491B2
公开(公告)日：2012-10-30
申请号：US12868909
申请日：2010-08-26
申请人： Derek C. Tao , Annie-Li-Keow Lum , Chung-Ji Lu
发明人： Derek C. Tao , Annie-Li-Keow Lum , Chung-Ji Lu
IPC分类号： G11C8/00
CPC分类号： G11C29/50012 , G11C11/41
摘要： A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed. The memory control circuitry is configured to set a clock based on the first signal.
摘要翻译： 半导体存储器段包括具有设置在第一跟踪列中的第一跟踪单元的第一存储体。 第二存储器组包括设置在第二跟踪列中的第二跟踪单元。 第一跟踪电路耦合到第一和第二跟踪单元，并且被配置为当第一和第二跟踪单元被访问时，将第一信号输出到存储器控制电路。 存储器控制电路被配置为基于第一信号设置时钟。
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公开(公告)号：US08942053B2
公开(公告)日：2015-01-27
申请号：US13535075
申请日：2012-06-27
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.
摘要翻译： 电路包括第一节点，第二节点，第一电流镜电路和第二电流镜电路。 第一电流镜电路具有参考端和镜像端。 第一电流镜电路的参考端耦合到第一节点，并且第一电流镜电路的镜像端耦合到第二节点。 第二电流镜电路具有参考端和镜像端。 第二电流镜电路的参考端耦合到第二节点，并且第二电流镜电路的镜像端耦合到第一节点。
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公开(公告)号：US08223571B2
公开(公告)日：2012-07-17
申请号：US12839575
申请日：2010-07-20
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
IPC分类号： G11C7/02
摘要： A circuit includes a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.
摘要翻译： 电路包括具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。
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公开(公告)号：US20120020176A1
公开(公告)日：2012-01-26
申请号：US12839575
申请日：2010-07-20
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
摘要： Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.
摘要翻译： 一些实施例涉及一种电路，包括：具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。
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7.发明授权Clock generators, memory circuits, systems, and methods for providing an internal clock signal 有权时钟发生器，存储器电路，系统和用于提供内部时钟信号的方法公开(公告)号：US08194495B2
公开(公告)日：2012-06-05
申请号：US12723077
申请日：2010-03-12
申请人： Derek C. Tao , Chung-Ji Lu , Annie-Li-Keow Lum
发明人： Derek C. Tao , Chung-Ji Lu , Annie-Li-Keow Lum
IPC分类号： G11C8/00
CPC分类号： G06F1/10 , G11C7/22 , G11C7/222 , G11C11/413
摘要： A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.
摘要翻译： 时钟发生器包括第一输入端和第二输入端。 第一输入端能够接收包括定义第一脉冲宽度的第一状态转变和第二状态转换的第一时钟信号。 第二输入端能够接收具有第三状态转换的第二时钟信号。 时间段从第一状态转换到第三状态转换。 时钟发生器可以比较第一个脉冲宽度和时间周期。 时钟发生器可以输出具有从第四状态转变到第五状态转变的第二脉冲宽度的第三时钟信号。 根据第一脉冲宽度与时间段的比较，第三时钟信号的第五状态转换能够被第一时钟信号的第二状态转换或第二时钟信号的第三状态转换触发。
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公开(公告)号：US20130088927A1
公开(公告)日：2013-04-11
申请号：US13253822
申请日：2011-10-05
申请人： Annie-Li-Keow Lum , Derek C. Tao , Bing Wang
发明人： Annie-Li-Keow Lum , Derek C. Tao , Bing Wang
CPC分类号： G11C7/222 , G11C11/412 , G11C11/413
摘要： A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro.
摘要翻译： 存储器宏接收到第一个时钟。 响应于第一时钟的第一时钟转换，产生第二时钟和第三时钟的第一转换。 跟踪信号的跟踪转换是由第二个时钟引起的。 基于第一时钟的第二时钟转换和跟踪信号的跟踪转变的稍后转换，产生第三时钟的第二转换。 第三个时钟由内存宏的输入输出使用。
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公开(公告)号：US09087565B2
公开(公告)日：2015-07-21
申请号：US13793815
申请日：2013-03-11
申请人： Annie-Li-Keow Lum , Derek C. Tao
发明人： Annie-Li-Keow Lum , Derek C. Tao
IPC分类号： G11C7/00 , G11C7/12 , G11C7/10 , G11C11/419
CPC分类号： G11C11/419 , G11C7/1048 , G11C7/12
摘要： A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver.
摘要翻译： 控制电路包括数据驱动器，充电电路和与数据驱动器和充电电路耦合的第一数据线。 所述充电电路被配置为当所述第一数据线被选择用于对与所述第一数据线相对应的存储单元进行访问时对所述第一数据线进行充电，并且当所述第一数据线未被选择用于访问所述存储器单元时， 。 基于第一控制信号的数据驱动器被配置为将第一数据线上的信号传送到数据驱动器的输出。
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公开(公告)号：US08913440B2
公开(公告)日：2014-12-16
申请号：US13253749
申请日：2011-10-05
IPC分类号： G11C7/10 , G11C11/419
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C11/419
摘要： A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
摘要翻译： 跟踪信号的跟踪边缘被激活。 基于跟踪信号的跟踪边缘，缓冲器被关闭并且锁存电路被接通。 缓冲器的缓冲器输出耦合到节点处的锁存电路的锁存器输出。 缓冲区接收一个内存宏的数据行。
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