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公开(公告)号：US07330798B2
公开(公告)日：2008-02-12
申请号：US11405432
申请日：2006-04-18
CPC分类号： G06F1/26 , G01R31/3004 , G01R31/31718 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.
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公开(公告)号：US07363176B2
公开(公告)日：2008-04-22
申请号：US11294431
申请日：2005-12-06
IPC分类号： G01R31/36
CPC分类号： G06F1/26 , G01R31/3004 , G01R31/31718 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.
摘要翻译： 通过以多个所需的时钟频率操作那些集成电路，并且为确定最小供电电压的那些频率中的每个频率来实现各个集成电路的电压分级，其产生一系列应用的测试向量的通过结果。
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公开(公告)号：US07142996B2
公开(公告)日：2006-11-28
申请号：US10912104
申请日：2004-08-06
CPC分类号： G06F1/26 , G01R31/3004 , G01R31/31718 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.
摘要翻译： 通过以多个所需的时钟频率操作那些集成电路，并且为确定最小供电电压的那些频率中的每个频率来实现各个集成电路的电压分级，其产生一系列应用的测试向量的通过结果。
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公开(公告)号：US20090019329A1
公开(公告)日：2009-01-15
申请号：US11826025
申请日：2007-07-11
IPC分类号： G01R31/3187
CPC分类号： G01R31/318508 , G01R31/318555
摘要： An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10, to the circuit block 38, 42, 44 in question and then back to the converter 10. Multiplexing circuitry 50, 52 associated with each serial scan chain loop 32, 34, 36 is used to either include that serial scan chain loop 32, 34, 36 in a combined serial scan chain or to bypass that serial scan chain loop 32, 34, 36. The circuit blocks 38, 42, 44 may be bypassed in this way if they are defective or if they are powered-down.
摘要翻译： 集成电路2包括多个电路块38,40,44，每个电路块具有从转换器10延伸到所讨论的电路块38,42,44的相关联的串行扫描链环32,34,36，然后回到 转换器10.与每个串行扫描链环32,34,36相关联的多路复用电路50,52用于在组合的串行扫描链中包括该串行扫描链环32,34,36或绕过该串行扫描链环 电路块38,42,44可以以这种方式被旁路，如果它们是有缺陷的或者它们被断电。
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公开(公告)号：US07734974B2
公开(公告)日：2010-06-08
申请号：US11826025
申请日：2007-07-11
IPC分类号： G01R31/28
CPC分类号： G01R31/318508 , G01R31/318555
摘要： An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10, to the circuit block 38, 42, 44 in question and then back to the converter 10. Multiplexing circuitry 50, 52 associated with each serial scan chain loop 32, 34, 36 is used to either include that serial scan chain loop 32, 34, 36 in a combined serial scan chain or to bypass that serial scan chain loop 32, 34, 36. The circuit blocks 38, 42, 44 may be bypassed in this way if they are defective or if they are powered-down.
摘要翻译： 集成电路2包括多个电路块38,40,44，每个电路块具有从转换器10延伸到所讨论的电路块38,42,44的相关联的串行扫描链环32,34,36，然后回到 转换器10.与每个串行扫描链环32,34,36相关联的多路复用电路50,52用于在组合的串行扫描链中包括该串行扫描链环32,34,36或绕过该串行扫描链环 电路块38,42,44可以以这种方式被旁路，如果它们是有缺陷的或者它们被断电。
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公开(公告)号：US07206982B1
公开(公告)日：2007-04-17
申请号：US10868342
申请日：2004-06-16
IPC分类号： G01R31/28
CPC分类号： G01R31/2884 , G01R31/3025
摘要： A diagnostic mechanism for an integrated circuit 2 uses a radio interface circuit 16 to provide communication between an external diagnostic device 22 and one or more diagnostic circuits 26, 28 within the integrated circuit 2. The use of a radio communication link for diagnostic data and control reduces the required pin count for the integrated circuit 2.
摘要翻译： 集成电路2的诊断机构使用无线电接口电路16来提供外部诊断装置22与集成电路2内的一个或多个诊断电路26,28之间的通信。 使用用于诊断数据和控制的无线电通信链路减少了集成电路2所需的引脚数。
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公开(公告)号：US07069376B2
公开(公告)日：2006-06-27
申请号：US10847371
申请日：2004-05-18
IPC分类号： G06F13/00
CPC分类号： G06F9/3867 , G06F9/3897 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A data processing apparatus and method of configuration of such an apparatus are provided, the apparatus comprising a plurality of logic elements for processing data, a plurality of storage elements for temporarily storing data, and a plurality of connections from which data is passed between the logic elements. Each connection comprises one or more path portions separated by the storage elements. A number of the storage elements are selectable storage elements having a bypass path associated therewith, and a controller is provided for controlling the selection of each selectable storage element or its associated bypass path based on setup information, in order to enable a change in the number of path portions within one or more of the connections. This hence allows some configurability of the connections within the apparatus post-production, with operating conditions and other aspects affecting operating speed being taken into account when producing the setup information used by the controller to determine which selectable storage elements to use, and which ones to bypass.
摘要翻译： 提供了一种用于配置这种装置的数据处理装置和方法，该装置包括用于处理数据的多个逻辑元件，用于临时存储数据的多个存储元件以及在该逻辑之间通过数据的多个连接 元素。 每个连接包括由存储元件分开的一个或多个路径部分。 多个存储元件是具有与其相关联的旁路路径的可选存储元件，并且提供控制器用于基于设置信息来控制对每个可选存储元件或其相关联的旁路路径的选择，以便能够改变数量 的一个或多个连接中的路径部分。 这因此允许设备后期制作中的连接的一些可配置性，当产生控制器使用的设置信息以确定使用哪些可选择的存储元件时，考虑到影响操作速度的操作条件和其他方面，以及哪些 旁路。
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公开(公告)号：US07005889B2
公开(公告)日：2006-02-28
申请号：US10887356
申请日：2004-07-09
IPC分类号： H03K19/0175
CPC分类号： G06F1/3203 , G06F1/3296 , H03K19/0185 , Y02D10/172
摘要： A data processing apparatus and method are provided for controlling level shifting. The data processing apparatus comprises a first component provided within a first voltage domain and operable to receive a first supply voltage, and a second component provided within a second voltage domain and operable to receive a second supply voltage. At least one of the first and second supply voltages are dynamically variable. The data processing apparatus further comprises an interface cell between the first and second voltage domains which is operable to receive a signal issued by the first component in the first voltage domain and destined for the second component. The interface cell comprises level shifting logic operable to convert the signal issued by the first component into a corresponding signal to be propagated to the second component in the second voltage domain. Further, bypass logic is provided which is operable in the event that the first supply voltage and second supply voltage are at the same voltage level to enable a bypass path around the level shifting logic such that the signal issued by the first component is propagated via the bypass path as the corresponding signal to the second component in the second voltage domain.
摘要翻译： 提供了一种用于控制电平转换的数据处理装置和方法。 数据处理装置包括设置在第一电压域内并可操作以接收第一电源电压的第一组件和设置在第二电压域内并可操作以接收第二电源电压的第二组件。 第一和第二电源电压中的至少一个是动态可变的。 数据处理装置还包括在第一和第二电压域之间的接口单元，其可操作以接收由第一电压域中的第一组件发出并发往第二组件的信号。 接口单元包括电平移位逻辑，可操作以将由第一分量发出的信号转换为在第二电压域中传播到第二分量的对应信号。 此外，提供了旁路逻辑，其可在第一电源电压和第二电源电压处于相同电压电平的情况下操作，以实现电平移位逻辑周围的旁路，使得由第一组件发出的信号经由 旁路路径作为与第二电压域中的第二分量相对应的信号。
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