Remapping data with pointer
    4.
    发明申请
    Remapping data with pointer 有权
    用指针重新映射数据

    公开(公告)号:US20120278651A1

    公开(公告)日:2012-11-01

    申请号:US13066976

    申请日:2011-04-28

    IPC分类号: G06F11/20

    CPC分类号: G06F11/20 G11C29/76

    摘要: Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block.

    摘要翻译: 本文的实施例涉及用于重新映射数据的方法。 在一个实施例中,确定第一存储器块是否有故障。 指针被存储到第一存储器块,并且当第一存储器块发生故障时,设置第一存储器块的指针标志。 先前存储在第一存储器块的数据被写入第二存储器块,其中指针指向第二存储器块的位置。

    ADAPTIVE MEMORY SYSTEM
    7.
    发明申请
    ADAPTIVE MEMORY SYSTEM 审中-公开
    自适应存储系统

    公开(公告)号:US20120272036A1

    公开(公告)日:2012-10-25

    申请号:US13092912

    申请日:2011-04-23

    IPC分类号: G06F12/06

    摘要: An adaptive, memory system is provided. The adaptive memory system has a number of physical-memory devices and a memory controller that creates and maintains a logical address space to which the physical-memory devices and data-storage allocations are mapped, and through which mapping the memory controller matches static, dynamic, and dynamically-adjustable retention and resiliency characteristics of portions of the physical-memory devices with specified retention and resiliency characteristics specified for the data-storage allocations.

    摘要翻译: 提供了一种自适应的存储系统。 自适应存储器系统具有多个物理存储器设备和存储器控制器,其创建并维护物理存储器件和数据存储器分配映射到的逻辑地址空间,并且存储器控制器通过映射将静态,动态 ,以及具有为数据存储分配指定的指定保留和弹性特性的物理存储器件的部分动态可调保留和弹性特性。

    ACCESSING MEMORY
    10.
    发明申请
    ACCESSING MEMORY 有权
    访问记忆

    公开(公告)号:US20150302904A1

    公开(公告)日:2015-10-22

    申请号:US14405904

    申请日:2012-06-08

    IPC分类号: G11C7/10 G06F13/16

    摘要: A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.

    摘要翻译: 所公开的示例性方法包括在至少第一和第二独立可选逻辑子列上执行同时数据访问,以经由存储器设备中的宽内部数据总线访问第一数据。 存储器件包括翻译缓冲器芯片,可独立选择的逻辑子级别的存储器芯片,将翻译缓冲器芯片连接到存储器控制器的窄的外部数据总线以及翻译缓冲器芯片和存储器芯片之间的宽内部数据总线 。 仅通过第一可独立选择的逻辑子级执行数据访问,以经由宽内部数据总线访问第二数据。 示例性方法还包括在单独的数据传输期间将第一数据的第一部分,第一数据的第二部分和窄的外部数据总线上的第二数据定位。