公开(公告)号：US5592063A

公开(公告)日：1997-01-07

申请号：US279918

申请日：1994-07-25

申请人： Dominique Savignac ,  Dieter Gleis ,  Manfred Menke

发明人： Dominique Savignac ,  Dieter Gleis ,  Manfred Menke

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C16/06 ,  H01L21/822 ,  H01L27/04 ,  G11C5/10

CPC分类号： G11C5/147 ,  G11C5/145

摘要： A voltage generator circuit includes a storage capacitor with a terminal for pickup of an output voltage. A voltage generator device which can be turned on and off has an output being connected to the terminal of the storage capacitor. A first comparator device which can be turned on and off compares the output voltage with a first threshold voltage and generates a signal for turning the voltage generator device on and off. A second comparator device compares the output voltage with a second threshold voltage and generates an output signal with which the first comparator device is turned on and off.

摘要翻译： 电压发生器电路包括具有用于拾取输出电压的端子的存储电容器。 可以接通和断开的电压发生器装置的输出端连接到存储电容器的端子。 可以接通和关断的第一比较器装置将输出电压与第一阈值电压进行比较，并产生用于使电压发生器装置接通和关断的信号。 第二比较器装置将输出电压与第二阈值电压进行比较，并产生与第一比较器装置接通和断开的输出信号。

公开(公告)号：US5327072A

公开(公告)日：1994-07-05

申请号：US839787

申请日：1992-02-21

申请人： Dominique Savignac ,  Manfred Menke ,  Dieter Gleis

发明人： Dominique Savignac ,  Manfred Menke ,  Dieter Gleis

IPC分类号： G06F15/78 ,  G05F3/20 ,  G11C5/14 ,  G11C11/407 ,  G11C11/408 ,  G11C11/413 ,  G05F3/16 ,  H03L1/00

CPC分类号： G05F3/205 ,  G11C5/146

摘要： A regulating circuit for a substrate bias voltage generator for generating a substrate bias voltage in an integrated semiconductor circuit includes a Schmitt trigger circuit disposed between a first potential and a second potential of a semiconductor circuit. The Schmitt trigger circuit has an output side and an input for controlling a hysteresis function of the Schmitt trigger circuit. An inverter array is connected downstream of the output side of the Schmitt trigger circuit. The inverter array is connected to the first potential and to a first supply potential of the semiconductor circuit in terms of supply voltage, and the inverter array has an output. The input of the Schmitt trigger circuit for controlling the hysteresis function of the Schmitt trigger circuit is connected to the output of the inverter array.

摘要翻译： 用于在集成半导体电路中产生衬底偏置电压的衬底偏置电压发生器的调节电路包括设置在半导体电路的第一电位和第二电位之间的施密特触发电路。 施密特触发电路具有输出端和用于控制施密特触发电路的滞后功能的输入端。 逆变器阵列连接在施密特触发电路输出侧的下游。 逆变器阵列在电源电压方面连接到半导体电路的第一电位和第一电源电位，并且逆变器阵列具有输出。 用于控制施密特触发电路的滞后功能的施密特触发电路的输入连接到逆变器阵列的输出。

公开(公告)号：US5546296A

公开(公告)日：1996-08-13

申请号：US279919

申请日：1994-07-25

申请人： Dominique Savignac ,  Dieter Gleis ,  Manfred Menke

发明人： Dominique Savignac ,  Dieter Gleis ,  Manfred Menke

IPC分类号： G11C11/407 ,  G11C5/14 ,  H02M3/07 ,  H03K19/00

CPC分类号： G11C5/145 ,  H02M3/073

摘要： A charge pump assembly includes a storage capacitor having one terminal for a first supply potential and another terminal for pickup of an output potential. The assembly has one charge pump or two charge pumps being controlled by push-pull signals. Each charge pump includes a p-channel MOS transistor having a gate terminal being controlled by a first signal and having a drain-to-source path with one terminal being connected to the other terminal of the storage capacitor. A sliding capacitor has one terminal being connected to the other terminal of the drain-to-source path of the p-channel MOS transistor and another terminal being controlled by a second signal. An n-channel MOS transistor has a gate terminal being controlled by a third signal and a drain-to-source path being connected between a second supply potential and the one terminal of the sliding capacitor. A pulse shaper device is supplied by an oscillator device for generating the signals, in such a way that the p-channel MOS transistor is conducting only whenever the second signal is at a high level, and the n-channel MOS transistor is conducting only whenever the second signal is at a low level.

摘要翻译： 电荷泵组件包括具有用于第一电源电位的一个端子和用于拾取输出电位的另一端子的存储电容器。 该组件具有一个电荷泵或两个电荷泵由推挽信号控制。 每个电荷泵包括一个p沟道MOS晶体管，其栅极端子由第一个信号控制，并具有一个漏极到源极通路，一个端子连接到存储电容器的另一个端子。 滑动电容器具有一个端子连接到p沟道MOS晶体管的漏极 - 源极通路的另一个端子，另一个端子由第二个信号控制。 n沟道MOS晶体管的栅极端子由第三信号控制，漏极 - 源极路径连接在第二电源电位和滑动电容器的一个端子之间。 脉冲整形器由用于产生信号的振荡器提供，使得只有当第二信号处于高电平时，p沟道MOS晶体管才导通，并且n沟道MOS晶体管仅在 第二信号处于低电平。

公开(公告)号：US5166546A

公开(公告)日：1992-11-24

申请号：US823860

申请日：1992-01-22

申请人： Dominique Savignac ,  Dieter Gleis ,  Brian Murphy

发明人： Dominique Savignac ,  Dieter Gleis ,  Brian Murphy

IPC分类号： H03K17/22

CPC分类号： H03K17/223

摘要： An integrated circuit for generating a reset signal includes terminals for a first and a second supply potential. A serial RC network is connected between the terminals. The RC network has an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between the components. An initializing circuit is connected parallel to the RC network. The initializing circuit has an output forming a second circuit node of the integrated circuit carrying a potential with a maximum value specified by dimensioning the initializing circuit, when the first supply potential is applied. An inverter circuit is connected between the first circuit node and the terminal for the second supply potential in terms of supply voltage. The inverter circuit has an input connected to the second circuit node and an output forming a third circuit node of the integrated circuit. A transistor has a source-to-drain path connected between the second circuit node and the terminal for the second supply potential and has a gate connected to the third circuit node. An additional inverter has an input at the third circuit node and an output forming a fourth circuit node of the integrated circuit at which a reset signal is present during operation.

摘要翻译： 用于产生复位信号的集成电路包括用于第一和第二电源电位的端子。 终端之间连接有一个串行RC网络。 RC网络具有连接在组件之间的集成电路的欧姆分量，电容分量和第一电路节点。 初始化电路与RC网络并联连接。 初始化电路具有形成集成电路的第二电路节点的输出，该第一电路节点在施加第一电源电位时承载具有由初始化电路的尺寸确定的最大值的电位。 在电源电压方面，逆变器电路连接在第一电路节点和用于第二电源电位的端子之间。 逆变器电路具有连接到第二电路节点的输入端和形成集成电路的第三电路节点的输出。 晶体管具有连接在第二电路节点和用于第二电源电位的端子之间的源极至漏极路径，并且具有连接到第三电路节点的栅极。 附加的反相器具有在第三电路节点处的输入和形成集成电路的第四电路节点的输出，在该输出端处在操作期间存在复位信号。

公开(公告)号：US5546036A

公开(公告)日：1996-08-13

申请号：US376683

申请日：1995-01-23

申请人： Diether Sommer ,  Dominique Savignac ,  Dieter Gleis

发明人： Diether Sommer ,  Dominique Savignac ,  Dieter Gleis

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/4093 ,  H03K3/286

CPC分类号： G11C11/4093 ,  G11C7/065 ,  G11C7/1051

摘要： A circuit array for amplifying and holding data with different supply voltages includes a first flip-flop being constructed in MOS technology for receiving a low supply voltage and data with a low supply voltage. The first flip-flop has output terminals. A second flip-flop being constructed in MOS technology receives a high supply voltage. The second flip-flop has a load segment and output terminals. At least one additional MOS transistor is connected in series with each of the output terminals of the second flip-flop between the load segment and ground. The at least one additional MOS transistor each has a gate terminal being connected to a respective one of the output terminals of the first flip-flip. A device for activating the first and second flip-flops is triggered for amplifying and holding the data to activate the first flip-flop and to activate the second flip-flop after a time delay.

摘要翻译： 用于放大和保持具有不同电源电压的数据的电路阵列包括以MOS技术构造的用于接收低电源电压的第一触发器和具有低电源电压的数据。 第一个触发器具有输出端子。 以MOS技术构造的第二个触发器接收高电源电压。 第二个触发器具有负载段和输出端。 至少一个额外的MOS晶体管与负载段和地之间的第二触发器的每个输出端串联连接。 所述至少一个附加MOS晶体管的每个栅极端子连接到第一翻盖的输出端子的相应一个。 触发用于激活第一和第二触发器的装置，用于放大和保持数据以激活第一触发器并在时间延迟之后激活第二触发器。

公开(公告)号：US20130058261A1

公开(公告)日：2013-03-07

申请号：US13406700

申请日：2012-02-28

申请人： Markus Balb ,  Dieter Gleis

发明人： Markus Balb ,  Dieter Gleis

IPC分类号： H04L12/26

CPC分类号： H04L29/06 ,  H04L47/266 ,  H04L69/32

摘要： The invention relates to a method, to a first and a second device (1, 2) and to a system (10) comprising the first and second device (1, 2) for transferring data, said system and devices matching the user data transfer rate during the data transfer between the first and the second device (1, 2). The first device (1) comprises in particular a medium access controller and operates in the second layer according to the OSI reference model, whilst the second device (2) transmits and receives user data in the first layer according to the OSI reference model and comprises an interface unit (24) for a DSL connection. The transfer rate match is achieved in particular by PAUSE frames according to the IEEE 802.3-2004 standard and the second device also operates in the second layer according to the OSI reference model to transmit and receive the PAUSE frames.

摘要翻译： 本发明涉及一种对第一和第二设备（1,2）和包括用于传送数据的第一和第二设备（1,2）的系统（10）的方法，所述系统和与用户数据传输相匹配的设备 在第一和第二设备（1,2）之间的数据传输期间的速率。 第一设备（1）特别包括介质访问控制器，并且根据OSI参考模型在第二层中操作，而第二设备（2）根据OSI参考模型在第一层中发送和接收用户数据，并且包括 用于DSL连接的接口单元（24）。 传输速率匹配特别是通过根据IEEE 802.3-2004标准的暂停帧来实现，并且第二设备还根据OSI参考模型在第二层中操作以发送和接收暂停帧。

公开(公告)号：US20080285479A1

公开(公告)日：2008-11-20

申请号：US11814478

申请日：2005-12-21

申请人： Markus Balb ,  Dieter Gleis

发明人： Markus Balb ,  Dieter Gleis

IPC分类号： G06F11/00

CPC分类号： H04L29/06 ,  H04L47/266 ,  H04L69/32

摘要： A method for transmitting data is disclosed, whereby data are transmitted in packets between a first device and a second device, whereby a further device disposed between the first device and the second device analyzes the packets at most for regeneration purposes. The second device transmits data between itself and a third device using DSL technology. During the data transmission between the first device and the second device a comparison of transmission rates takes place.

摘要翻译： 公开了一种用于发送数据的方法，由此在第一设备和第二设备之间以数据分组的形式发送数据，从而设置在第一设备和第二设备之间的另一设备最多分析数据包以用于再生目的。 第二设备使用DSL技术在其与第三设备之间传输数据。 在第一设备和第二设备之间的数据传输期间，发生传输速率的比较。

公开(公告)号：US08125924B2

公开(公告)日：2012-02-28

申请号：US11814478

申请日：2005-12-21

申请人： Markus Balb ,  Dieter Gleis

发明人： Markus Balb ,  Dieter Gleis

IPC分类号： G01R31/08

CPC分类号： H04L29/06 ,  H04L47/266 ,  H04L69/32

摘要： A method for transmitting data is disclosed, whereby data are transmitted in packets between a first device and a second device, whereby a further device disposed between the first device and the second device analyzes the packets at most for regeneration purposes. The second device transmits data between itself and a third device using DSL technology. During the data transmission between the first device and the second device a comparison of transmission rates takes place.

摘要翻译： 公开了一种用于发送数据的方法，由此在第一设备和第二设备之间以数据分组的形式发送数据，从而设置在第一设备和第二设备之间的另一设备最多分析数据包以用于再生目的。 第二设备使用DSL技术在其与第三设备之间传输数据。 在第一设备和第二设备之间的数据传输期间，发生传输速率的比较。

公开(公告)号：US20100238918A1

公开(公告)日：2010-09-23

申请号：US11813988

申请日：2005-12-23

申请人： Dieter Gleis ,  Pidder Kassel ,  Mathias Riess

发明人： Dieter Gleis ,  Pidder Kassel ,  Mathias Riess

IPC分类号： H04L12/66

CPC分类号： H04L29/06 ,  H04L69/32

摘要： The invention relates to a method and a device for transmitting data, wherein when transmitting data with DSL technology transmission rates are compared.

摘要翻译： 本发明涉及一种用于传输数据的方法和装置，其中当用DSL技术传输数据时传输速率进行比较。