公开(公告)号：US5249286A

公开(公告)日：1993-09-28

申请号：US982031

申请日：1992-11-24

申请人： Donald B. Alpert ,  Oved Oz ,  Gideon Intrater ,  Reuven Marko ,  Alon Shacham

发明人： Donald B. Alpert ,  Oved Oz ,  Gideon Intrater ,  Reuven Marko ,  Alon Shacham

IPC分类号： G06F12/12

CPC分类号： G06F12/126

摘要： A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.

摘要翻译： 一种微处理器架构，其包括将单个条目锁定到其集成指令高速缓存和数据高速缓存中的能力，同时使缓存的其余部分被解锁并可用于捕获微处理器的动态参考位置。 微处理器还包括锁定指令高速缓存条目的能力，而不需要在锁定过程期间执行指令。

公开(公告)号：US5481751A

公开(公告)日：1996-01-02

申请号：US323586

申请日：1994-10-17

申请人： Donald B. Alpert ,  Dror Avnon ,  Amos Ben-Meir ,  Ran Talmudi

发明人： Donald B. Alpert ,  Dror Avnon ,  Amos Ben-Meir ,  Ran Talmudi

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/382 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3885

摘要： A microprocessor partially decodes instructions retrieved from main memory before placing them into the microprocessor's integrated instruction cache. Each storage location in the instruction cache includes two slots for decoded instructions. One slot controls one of the microprocessor's integer pipelines and a port to the microprocessor's data cache. A second slot controls the second integer pipeline or one of the microprocessor's floating point units. The instructions retrieved from main memory are decoded by a loader unit which decodes the instructions from the compact form as stored in main memory and places them into the two slots of the instruction cache entry according to their functions. In addition, auxiliary information is placed in the cache entry along with the instruction to control parallel execution as well as emulation of complex instructions. A bit in each instruction cache entry indicates whether the instructions in the two slots are independent, so that they can be executed in parallel, or dependent, so that they must be executed sequentially. Using a single bit for this purpose allows two dependent instructions to be stored in the slots of the single cache entry.

摘要翻译： 微处理器在将它们放入微处理器的集成指令高速缓存之前部分解码从主存储器检索的指令。 指令高速缓存中的每个存储位置包括用于解码指令的两个时隙。 一个插槽控制微处理器的整数管道之一和微处理器数据高速缓存的端口。 第二个插槽控制第二个整数流水线或微处理器的浮点单元之一。 从主存储器检索的指令由加载器单元解码，该加载器单元根据存储在主存储器中的紧凑形式对指令进行解码，并根据它们的功能将它们放入指令高速缓存条目的两个时隙中。 此外，辅助信息与控制并行执行的指令以及复杂指令的仿真一起被放置在高速缓存条目中。 每个指令高速缓存条目中的一位指示两个时隙中的指令是否是独立的，以便它们可以并行执行或依赖执行，以便它们必须顺序执行。 为了这个目的使用单个位允许将两个相关指令存储在单个缓存条目的插槽中。

公开(公告)号：US5617554A

公开(公告)日：1997-04-01

申请号：US372805

申请日：1994-12-23

申请人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

发明人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F2212/652

摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.

摘要翻译： 这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。 可以选择不同的内存大小和不同的页面大小。 地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。 地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。 线性地址到字段的格式取决于所选的内存大小和所选的页面大小。 对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组 的页表条目。 表中条目的大小取决于所选的内存大小。 表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。

公开(公告)号：US5958037A

公开(公告)日：1999-09-28

申请号：US023916

申请日：1993-02-26

申请人： Robert S. Dreyer ,  William M. Corwin ,  Donald B. Alpert ,  Tsu-Hua Wang ,  Daniel G. Lau ,  Frederick J. Pollack

发明人： Robert S. Dreyer ,  William M. Corwin ,  Donald B. Alpert ,  Tsu-Hua Wang ,  Daniel G. Lau ,  Frederick J. Pollack

IPC分类号： G06F15/78 ,  G06F1/00 ,  G06F9/30 ,  G06F9/445 ,  G06F11/00 ,  G06F21/00 ,  G06F9/22

CPC分类号： G06F21/73 ,  G06F11/006 ,  G06F9/30003 ,  G06F9/328 ,  G06F9/44505 ,  G06F2207/7219

摘要： A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

摘要翻译： 一种用于提供至少两种类型的识别信息的多级识别装置和方法，所述识别信息包括用于识别微处理器的来源的第一类型和可用的识别信息的级数，以及用于识别家族的第二类型，模型 ，步进ID，以及微处理器的功能。 该装置包括用于存储识别微处理器原点的标记串的第一存储元件。 该装置还包括用于存储包括特定识别微处理器的数据字段的其它微处理器ID数据的第二存储器元件。 该装置包括用于执行读取指示字符串或微处理器ID数据的ID指令的控制逻辑，这取决于预选类型。 无论读取哪个识别信息，它被存储在一个或多个通用寄存器中，以供程序员选择读取。 该方法在微处理器运行时随时可用。

公开(公告)号：US5692167A

公开(公告)日：1997-11-25

申请号：US697028

申请日：1996-08-19

申请人： Edward T. Grochowski ,  Donald B. Alpert

发明人： Edward T. Grochowski ,  Donald B. Alpert

IPC分类号： G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30192 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3861 ,  G06F9/3867

摘要： An apparatus and method for improving the performance of pipelined computer processors which have segment bits for specifying the operand size, the address size for memory reference, and the stack size, and which can run self-modifying code. The processor predicts segment bits based on previously used segment bits. Actual segment bits are later determined during execution of an instruction. The predicted segment bits are compared with the actual segment bits, and the pipeline is flushed if they do not match. Also, an instruction verification method is provided to determine if self-modifying code has modified instructions already in the pipeline. Upon execution of a write instruction, each instruction address in the pipeline is compared with the write address. If a match is found, the pipeline is flushed.

摘要翻译： 一种用于提高流水线计算机处理器的性能的装置和方法，其具有用于指定操作数大小的段位，存储器引用的地址大小和堆栈大小，并且可以运行自修改代码。 处理器根据先前使用的段位来预测段位。 稍后在执行指令期间确定实际分段位。 将预测的段位与实际段位进行比较，如果管道不匹配，则将其清除。 此外，提供了一种指令验证方法来确定自修改代码是否具有已经在流水线中的修改的指令。 在执行写入指令时，将流水线中的每个指令地址与写入地址进行比较。 如果找到匹配，管道将被刷新。

公开(公告)号：US5669011A

公开(公告)日：1997-09-16

申请号：US665586

申请日：1996-06-18

申请人： Donald B. Alpert ,  Dror Avnon ,  Amos Ben-Meir ,  Ran Talmudi

发明人： Donald B. Alpert ,  Dror Avnon ,  Amos Ben-Meir ,  Ran Talmudi

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/382 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3885

摘要： A microprocessor partially decodes instructions retrieved from main memory before placing them into the microprocessor's integrated instruction cache. Each storage location in the instruction cache includes two slots for decoded instructions. One slot controls one of the microprocessor's integer pipelines and a port to the microprocessor's data cache. A second slot controls the second integer pipeline or one of the microprocessor's floating point units. The instructions retrieved from main memory are decoded by a loader unit which decodes the instructions from the compact form as stored in main memory and places them into the two slots of the instruction cache entry according to their functions. In addition, auxiliary information is placed in the cache entry along with the instruction to control parallel execution as well as emulation of complex instructions. A bit in each instruction cache entry indicates whether the instructions in the two slots are independent, so that they can be executed in parallel, or dependent, so that they must be executed sequentially. Using a single bit for this purpose allows two dependent instructions to be stored in the slots of the single cache entry.

摘要翻译： 微处理器在将它们放入微处理器的集成指令高速缓存之前部分解码从主存储器检索的指令。 指令高速缓存中的每个存储位置包括用于解码指令的两个时隙。 一个插槽控制微处理器的整数管道之一和微处理器数据高速缓存的端口。 第二个插槽控制第二个整数流水线或微处理器的浮点单元之一。 从主存储器检索的指令由加载器单元解码，该加载器单元根据存储在主存储器中的紧凑形式对指令进行解码，并根据它们的功能将它们放入指令高速缓存条目的两个时隙中。 此外，辅助信息与控制并行执行的指令以及复杂指令的仿真一起被放置在高速缓存条目中。 每个指令高速缓存条目中的一位指示两个时隙中的指令是否是独立的，以便它们可以并行执行或依赖执行，以便它们必须顺序执行。 为了这个目的使用单个位允许将两个相关指令存储在单个缓存条目的插槽中。

公开(公告)号：US5475824A

公开(公告)日：1995-12-12

申请号：US386595

申请日：1995-02-10

申请人： Edward T. Grochowski ,  Kenneth D. Shoemaker ,  Ahmad Zaidi ,  Donald B. Alpert

发明人： Edward T. Grochowski ,  Kenneth D. Shoemaker ,  Ahmad Zaidi ,  Donald B. Alpert

IPC分类号： G06F9/28 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3822 ,  G06F9/30149 ,  G06F9/3853 ,  G06F9/3885

摘要： A computer system includes a dual instruction decoder which issues two instructions in parallel within a single clock cycle if their are no register dependencies between the instructions, and instructions fall within a predetermined subset of the complete instruction set. The system includes first and second instruction pipelines. The first pipeline executes any instruction issued from the full instruction set, while the second pipeline only executes a predetermined subset of instructions selected based on principles of locality. A register dependency checker determines whether the destination register of a first instruction is used during the execution of a second instruction in an instruction sequence. When both instructions are within the subset and there are no dependencies, the first and second instructions can be issued in parallel in the first and second pipelines.

摘要翻译： 计算机系统包括双指令解码器，如果它们在指令之间没有寄存器依赖性，并且指令落入完整指令集的预定子集内，则在单个时钟周期内并行地发出两个指令。 该系统包括第一和第二指令管线。 第一个流水线执行从完整指令集发出的任何指令，而第二个流水线仅执行基于局部性原则选择的预定指令子集。 寄存器依赖性检查器确定在执行指令序列中的第二指令期间是否使用第一指令的目的地寄存器。 当两个指令都在子集内并且没有依赖性时，可以在第一和第二管道中并行地发出第一和第二指令。

公开(公告)号：US5263153A

公开(公告)日：1993-11-16

申请号：US573287

申请日：1990-08-24

申请人： Amos Intrater ,  Donald B. Alpert

发明人： Amos Intrater ,  Donald B. Alpert

IPC分类号： G06F11/36 ,  G06F11/30

CPC分类号： G06F11/3636

摘要： A method for monitoring the sequence of instructions executed by a central processing unit. When a branch instruction is executed, the central processing unit generates a representative interface signal. When a jump instruction is executed or an exception occurs, the central processing unit displays representative information on the external memory interface.

摘要翻译： 一种用于监视由中央处理单元执行的指令序列的方法。 当执行分支指令时，中央处理单元生成代表性的接口信号。 当执行跳转指令或发生异常时，中央处理单元在外部存储器接口上显示代表性信息。

公开(公告)号：US4802085A

公开(公告)日：1989-01-31

申请号：US6012

申请日：1987-01-22

申请人： Simon J. Levy ,  Donald B. Alpert

发明人： Simon J. Levy ,  Donald B. Alpert

IPC分类号： G06F9/38 ,  G06F13/14 ,  G06F3/00

CPC分类号： G06F9/3824 ,  G06F9/3861

摘要： A method for detecting and handling memory-mapped I/O in a pipelined data processing system is provided. The method uses two signals on the system interface: when the system generates a read bus cycle, it activates an output signal if certain I/O requirements are not satisfied; an input signal is activated when the reference is to a peripheral device that exhibits certain characteristics; when the system detects that both the input signal and the output signal are active, it discards the data read during the bus cycle, serializes instruction execution and regenerates the read bus cycle, this time satisfying the requirements for I/O such that the output signal is driven inactive.

摘要翻译： 提供了一种在流水线数据处理系统中检测和处理存储器映射的I / O的方法。 该方法在系统接口上使用两个信号：当系统产生读总线周期时，如果不满足某些I / O要求，则激活输出信号; 当参考具有某些特性的外围设备时，输入信号被激活; 当系统检测到输入信号和输出信号都有效时，丢弃在总线周期中读取的数据，串行化指令执行并重新生成读总线周期，此时满足I / O要求，使输出信号 被驱动无效。

公开(公告)号：US5802605A

公开(公告)日：1998-09-01

申请号：US756184

申请日：1996-11-25

申请人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

发明人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F2212/652

摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.

摘要翻译： 这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。 可以选择不同的内存大小和不同的页面大小。 地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。 地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。 线性地址到字段的格式取决于所选的内存大小和所选的页面大小。 对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组 的页表条目。 表中条目的大小取决于所选的内存大小。 表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。